AT&S (Austria)

Abstract This paper presents use cases to demonstrate the advances in simulation, prognostic health management and digital twins, and power electronics for electric vehicles and gives an insight into the potential for the end users in the future.

This paper explores the potential of the modified semi-additive process (mSAP) for precise manufacturing and measurement of structures on printed circuit boards (PCBs), with a particular emphasis on high-frequency applications. One example discussed in this paper is the measurement of a substrate-integrated waveguide (SIW) loaded with mushroom metasurface unitcells. Given the high sensitivity of metasurface structures to fabrication errors, this serves as a relevant case study. Our invetigation includes a detailed evaluation, incorporating X-ray analysis, a cross-sectional analysis, and S-parameters measurements up to 150 GHz using customized multiline thru-reflect-line (TRL) with uncertainty analysis. The measurement results show strongly agree with electromagnetic(EM) simulation, highlighting the suitability of mSAP technology for accurate fabrication and enabling measurement of high-frequency devices.

This paper presents an experimental characterization of grounded coplanar waveguides (GCPWs) with uncertainty analysis. GCPW lines to be analyzed were fabricated using different subtractive printed circuit board (PCB) manufacturing processes: panel plating method and pattern plating method. Using a modified multiline method, we have extracted the propagation constants with uncertainty propagation analysis. This considered instrumentation noise, length uncertainty, and impedance mismatch caused by variations in cross-section due to the fabrication capabilities of each manufacturing process. By reformulating the propagation constant, we obtained the attenuation per unit length and the effective relative permittivity as a function of frequencies up to 43.5GHz with 95% confidence interval. These results showed good agreement with full-wave simulations and highlighted the differences between the PCB manufacturing processes.

To accommodate the ever-growing data requirements in densely populated areas and address the need for high-resolution sensing in diverse next-generation applications, there is a noticeable trend towards utilizing large unallocated frequency bands above 100 GHz. To overcome the harsh propagation conditions, large-scale antenna arrays are crucial and urge the need for cost-effective, mass-manufacturable technologies. A dedicated Any-Layer High Density Interconnect PCB technology for highly efficient wireless D-band (110–170 GHz) systems is proposed. Specifically, the adapted stack accommodates broadband air-filled substrate-integrated-waveguide components for efficient long-range signal distribution and low-loss passives. The viability of the suggested technology platform is demonstrated by designing, fabricating and measuring several essential low-loss air-filled substrate-integrated-waveguide components, such as a dual rectangular filter, with a minimal insertion loss of 0.87 dB and 10 dB-matching within the (132.8–139.2 GHz) frequency band, and an air-filled waveguide with a routing loss of only 0.08 dB/mm and a flat amplitude variation within 0.01 dB/mm over the (115–155 GHz) frequency range. A broadband transition towards stripline, with a limited loss of 1.1 dB, is described to interface these waveguides with compactly integrated chips. A tolerance analysis is included as well as a comparison to the state of the art.

This paper investigates the bandwidth extension achieved for a Doherty power amplifier topology, by using a packaging approach which minimizes packaging-related parasitic effects, such as the effective inductance of bonding wires. A Doherty power amplifier module is designed using a novel packaging approach by embedding the higher power RF transistors inside the module laminate. This embedded approach is compared against a more conventional previously developed demonstrator, which uses wire-bonded transistor dies. Initial simulations show that the embedded Doherty amplifier can extend the bandwidth from the initial 500 MHz to 800 MHz, while maintaining similar levels of output power, drain efficiency and transducer gain. Finally, the measured performance of the embedded and wire-bonded demonstrators is also analyzed and compared.

A 28 GHz air-filled cavity-backed microstrip antenna array, which is embedded in a polyphenyl ethers (PPE)-based multilayer printed circuit board (PCB), is presented. The air cavity is implemented by a novel 2.5D PCB process with a no-flow prepreg, to improve radiation efficiency, bandwidth, and directivity while maintaining a low profile. A four-element antenna array was designed, simulated, and measured. The measurement results yield a bandwidth of 3.8% centered at 28.5 GHz and a realized gain of 14.8 dBi with the antenna substrate thickness of <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$0.035\lambda_{0}$</tex> and the separation of <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$0.8\lambda_{0}$</tex> between elements. Network analysis for a single patch section of the designed antenna with transmission line (TL) models is discussed as well. The comparison between the analyzed, simulated, and measured input impedance shows a good agreement over the given frequency band.

Surface Mounted Devices (SMDs) are widely spread throughout microelectronics and power electronics. They mostly employ epoxy molding compound (EMC) based encapsulations. Thus, enhanced lifetime assessment methods are necessary. To understand the stress situation in SMDs at the end of the production cycle, an improved model approach for the curing of EMC is implemented within Finite Element Analysis (FEA) simulations. During production in e.g a RTM process, material properties are spatially varying due to different curing degrees. Hence, a mismatch of mechanical properties is present, which in return leads to internal stresses. The introduced model approach is an extension to the work of Gschwandl. et al [1] and includes a stress-free deformation before vitrification, changing material properties during curing as well as plastic deformations and visco-elastic effects. The implementation in numerical FEA simulations allows for a better understanding of arising residual stresses and help optimizing the production cycle of SMDs.

Regarding printed circuit board industry, panel level warpage is a fundamental issue leading to problems regarding both producibility of the printed circuit boards at manufacturer side and reliability of the final products at customer side. Embedded component technology is particularly affected by warpage issues due to asymmetric stack-ups and the mismatch in mechanical and thermal material properties of the board materials and the embedded silicon dies. Consequently, finite element simulations of printed circuit board warpage on panel level are becoming increasingly important; identifying unsuitable board designs and stack-ups prior to manufacturing prevents warpage related problems in the first place and thus efficiently saves resources as well as production time and costs. The current study deals with finite element simulations of printed circuit boards comprising electrical components to identify the remaining board warpage after cooling down from lamination temperature.Understanding the main factors influencing the warpage behavior and how to take them into account by simulation is crucial for achieving reliable simulation results. Next to the mismatch in the coefficient of thermal expansion of the different materials, cure-induced resin shrinkage turned out to be a main driver of printed circuit board warpage. Our main focus is therefore on material testing and the correct implementation of the measured material properties into the finite element software Abaqus/CAE. A measurement method was developed which allows to measure the cure shrinkage of pure resin samples using thermo-mechanical analysis. The measured shrinkage was implemented into the material model of the resin and is thus considered in simulation, as well as temperature-dependent thermal and mechanical properties of all materials and the orthotropic behavior of the fiber-reinforced composites.A 3-D model of a printed circuit board was created in Abaqus/CAE using conventional shell elements. The stack-up was implemented as a composite layup, considering all copper and FR4 layers, the electrical dies and the pure resin enclosing the dies. A predefined temperature field represents the actual temperature conditions in the press, starting at lamination temperature and cooling down to room temperature after curing. During the first step at high temperatures, cure shrinkage is applied to the resin, representing the curing of the resin-based constituents of the board in the press; applying the resin shrinkage already leads to a first deviation from the initial flat and stress-free condition. Driven by the differences in the coefficient of thermal expansion of all the materials, the deformation increases during the second step while cooling, until at room temperature the final warped state is reached. The maximum deformation at the corners of the model was then evaluated with regard to the initial flat state.Comparison of the simulation results and the measurement values of warped boards shows very good agreement. The overall panel warpage as well as the deformation of the individual arrays positioned on the panel could be predicted with sufficient accuracy. Variations in the stack-up of the board in order to reduce warpage were modeled as well, the simulation results showing the same trend in warpage behavior as the boards actually produced. Based on these results it could be shown that the presented simulation approach is suitable for describing warpage of printed circuit boards on panel level.

In manufacturing of electronic packages, especially modules manufactured in a panel level based packaging process, the occurring package warpage is always one of the most critical issues. The deformation of manufactured packages is generally triggered by dimensional changes in the material layers due to thermal expansion and chemical shrinkage during the curing process. Being able to predict the occurring warpage can significantly improve design quality and reliability of electronic systems. The current study deals with the application of finite element simulation to predict the warpage after manufacturing and singularization of a fine line structured multi-die package manufactured in a panel level packaging process. For defining the material properties of the applied dielectric materials, temperature dependent linear elastic models were applied considering the temperature dependency of the materials as well as their orthotropy were applicable. For b-staged resins, a coefficient of chemical shrinkage was determined and implemented in the material model. Copper properties were modelled considering temperature dependency and plasticity while directional effects in copper were neglected. All applied material models have been determined in the course of the project. The package structure was modelled in ABAQUS ®, one of the industry standard multi-physics simulation packages, applying a homogenization approach resulting in a rather small but still accurate model of the package. The boundary conditions were specified based on the actual manufacturing conditions in the production line of the package. Finally the calculated, resulting deformation of the package was compared to the actually measured deformation of the packages, where cross-sectioning profilometry, Shadow Moire methodology and X-ray tomography and have been applied to create the validation data. Based on the presented results it could be shown that the applied finite element simulation approach is suitable for describing the warpage occurring during panel level packaging of electronic modules.