American Semiconductor (United States)

Heterogeneous integration for system in package (SiP), flip-chip integration in 3D packaging and embedded ICs in advanced Printed Circuit Boards (PCB) are all pushing the limits for low profile packaging. Advanced polymer materials applied in Semiconductor-on-Polymer™ wafer level chip scale packaging (SoP WLCSP) are gaining traction as a high reliability ultra-thin packaging solution. The 2019 roadmap for Heterogeneous Integration defines heterogeneous Integration (HI) as the integration of separately manufactured components into a higher-level assembly that provides enhanced functionality and improved operating characteristics. The development of this technology is a significant industry challenge that can evolve quickly with the application of SoP polymer based packaging. At advanced nodes, die yield falls exponentially with die size. Splitting a large monolithic SoC into smaller tightly coupled die, is an attractive alternative considering that die cost per unit area is escalating. The smartphone industry has been an early adopter of HI technologies in the use of SiP for multiple generations, essentially for the advantages in miniaturization, modularity for co-design, and enhanced generation-over-generation performance. The application processor is almost always on the most advanced node and housed in a Package on Package (PoP) configuration with memory component(s) stacked on top of this ASIC. Teardowns of the Package-on-Package (PoP) packages for Apple XSMax, Samsung Galaxy S9+, and Huawei 20 Pro have shown the utilization and need for continued z-axis thickness scaling. Implementation of SoP CSP for package in package integration or for chip on thin PCB, interposer or flex can provide another package capability for evolution of multi-layer heterogeneous integration. Reliable ultra-thin polymerized die have the potential to tackle the third dimension (z-axis) of total IC package volume in 3D integration. SoP die can replace current full thickness or partially thinned (typically >250µm) die with <35µm package thickness devices. In addition, the SoP process has the potential to extend package roadmaps enabling smaller higher performance packages in several areas, including Fan-Out (FO). Thin bridge die could simplify localized high IO for substrates. Thin embedded IPD (integrated passive devices) have the potential to increase the capability and shrink the size of substrate process based passives, similar to the performance increase for wafer based devices versus printed electronics. In addition thin high IO die could allow simplified embedding in substrates. The differentiation of PCBs, interposers and flex circuits is starting to blur. Package integration within the layers of these devices can create embedded ICs that take less system space and improve system performance. Traditionally, manufacturing steps to place an IC within the board substrate vary and require space to be created for the component body, in the form of a cavity for traditional packaged ICs. In Integrated module board (IMB), components are aligned and placed inside a cavity that is routed to the core laminate by controlled-depth routing. The cavity is filled with molding polymer to ensure chemical, mechanical, and electrical compatibility with the substrate. Isotropic solder is impregnated with the polymer to form reliable solder joints when the embedded part is laminated into the stack. Polymerized ICs in SoP CSP eliminate cavity requirements and molding polymers for IMB. Chip in polymer (CIP) approaches use thin chips in built up dielectric layers of PCBs, rather than integrating them into the core layers. When SoP CSP is applied, it is feasible to achieve the same capability, but with a much smaller z-axis and without creating a surface geography perturbation. This presentation will include an introduction to SoP CSP utilizing advanced polymer technology for accelerating evolution of HI, PoP and Embedded applications.

Noninvasive sensors capable of measuring weak biopotential signals, such as electrocardiogram (ECG) and EEG, and communicating results wirelessly to a host computer are developing rapidly. Some of them utilize capacitively coupled electrodes in an attempt to place the sensor at a distance from the skin. This article demonstrated the fabrication and development of a capacitively coupled ECG electrode prototype using custom high specific capacitance electrodes and custom high-performance electronics. Two ultrathin capacitive electrodes were fabricated on a flexible polyimide substrate (2 × 2 in) protected by a guard ring to reduce noise. The detection and amplification circuitry consisted of operational amplifiers (OpAmps) that filtered and conditioned the ECG signal. R-peaks in the ECG were readily detected and quantified using both simulated signals from ECG databases and real signals from human subjects. Heart rates and heart rate variability calculated from our monitor measurements were comparable with commercial rigid wearable sensors, including a smartwatch and an ECG monitor that uses standard clinical ionic electrodes. The prototype monitor was tested on human subjects during rest and moderate exercise and showed appropriate responses. The challenge of high-gain low-noise amplification was met by the development of highly thinned OpAmps whose operation was shown to be equivalent to commercially available rigidly packaged OpAmps, demonstrating that high-performance Si-electronics can be used to produce high-fidelity signals from weak biopotentials.

Flexible Hybrid Electronics combine the best characteristics of printed electronics and silicon ICs to create high performance, ultra-thin, physically flexible systems. New static and dynamic tests are being developed to evaluate the performance of these systems. Dynamic radius of curvature and torsional test results are presented for a flexible hybrid electronics system with a FleX Silicon-on-Polymer operational amplifier manufactured in an 180nm CMOS process with 4-levels of metal interconnect mounted on a PET substrate.

Lamination-reinforced Bi2223/Ag (1 G) HTS tapes with mechanical and electrical properties tailored for applications have been developed by applying a strain compensation model and statistical analysis to material selection and lamination optimization. Stainless steel reinforced wire has been established with double-bend tolerance improved to 38 mm diameter from 50 mm, tensile strain tolerance improved to 0.4% from 0.35% and 10% higher current density. For applications requiring high-current windings, a prototype reinforced wire has been developed with two co-laminated HTS tapes and double the standard critical current (to 255 A at 77 K). Brass laminated hermetic 1 G wire has also been established for cable applications with over 200 km manufactured and shipped. A wide range of brass tempers can be used to tailor mechanical properties for different requirements. Reliable capability for producing low resistance, robust hermetic splices has been qualified for brass laminated wire in order to efficiently make custom long length wires and repair wire in the field or during manufacture of applications such as cables.

Significant enhancements in flux-pinning were obtained for Dy-doped, YBCO films via a metalorganic deposition (MOD) process on rolling-assisted biaxially textured substrates (RABiTS). It has been reported previously that incorporation of excess rare-earth ions during the MOD process, results in improvement of J <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">c</sub> for H//c, however, a decrease in J <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">c</sub> for H//ab is observed. We report here that by altering the processing conditions the reduction in the magnitude of the current peak for H//ab can be minimized while significantly enhancing the random pinning at all field orientations. The result is a YBCO film with significantly reduced anisotropy compared to the typical YBCO films prepared by the MOD process. This is accomplished by incorporating both a high density of stacking faults and (Dy, Y) <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> nanoparticles which result in the strong pinning for H//ab and a broad pinning peak for H//c respectively.

The metal organic deposition (MOD) of YBCO high temperature superconducting films on RABiTS (rolling assisted biaxially textured substrates) templates has been developed at American Superconductor as a low-cost, scalable manufacturing process for the commercialization of the second generation (2G) HTS wire. The MOD process is based on the deposition of a triflu-oroacetate (TFA) based metal organic precursor film which is converted, in an ex-situ process, to the superconducting YBCO film. A major goal of the development has been achieving high critical currents. This paper reports the preparation and characterization of MOD-YBCO films with critical currents exceeding 500 A/cm-w (77 K, self-field) using a scaleable thick film approach on RABiTS templates. The high critical current films were obtained through optimization of the precursor composition, nucleation and growth conditions. The through-thickness dependence of the critical current density of MOD Alms as a function of film thickness and a correlation of the through-thickness transport properties and microstructure of the thick MOD/RABiTS samples is reported.

Key features of the microstructure in high critical current density ( <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">J_C </i> ) MOD Y <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1</sub> Ba <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> Cu <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">y</sub> (YBCO) films on biaxially-textured nickel substrates with intervening buffer layers are presented. 0.8 <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">mu</i> m thick MOD YBCO films on the 4cm wide RABiTS templates have 77K, self-field <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">J_C </i> and <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">I_C </i> values exceeding 3 MA/cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and 250A/cm-width, respectively. MOD YBCO films have a laminar grain structure with a high density of YBa <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> Cu <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">4</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">y</sub> (Y124) intergrowths, which give rise to an enhanced peak in angular anisotropy measurements of <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">J_C </i> when the applied field is parallel to the ab planes of the YBCO films. Other key aspects of MOD YBCO films related to the laminar growth mode and layered microstructure are grain boundary overgrowth, grain boundary meandering, colony microstructures, incoherent precipitates of Y <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> and Y <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> Cu <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">5</sub> , and phase separations.

The US Department of Energy is currently funding the design, development and demonstration of the first long length, transmission level voltage, cold dielectric, high temperature superconductor power cable. The cable is designed for permanent installation in the long island power authority (LIPA) grid and will be able to carry 574 MVA at a voltage of 138 KV. The project is led by American Superconductor and the team is comprised of Nexans, Air Liquide and LIPA. This paper will describe the goals of the project, an overview of the cable design, refrigeration system and site design. It will also include the statistics of the HTS wire manufactured for this project, the results of the qualification testing on a prototype 30 meter cable and the preparation work of the refrigerator system. The cable will be completed and put into service in the LIPA grid in 2007.

The United States is presently served by Class-A, -B and -C low-level radioactive waste and naturally-occurring and accelerator-produced radioactive material disposal sites in Washington and South Carolina; a Class-A and mixed waste disposal site in Utah that also accepts naturally-occurring radioactive material; and hazardous and solid waste facilities and uranium mill tailings sites that accept certain radioactive materials on a site-specific basis. The Washington site only accepts low-level radioactive waste from 11 western states due to interstate Compact restrictions on waste importation. The South Carolina site will be subject to geographic service area restrictions beginning 1 July 2008, after which only three states will have continued access. The Utah site dominates the commercial Class-A and mixed waste disposal market due to generally lower state fees than apply in South Carolina. To expand existing commercial services, an existing hazardous waste site in western Texas is seeking a Class-A, -B and -C and mixed waste disposal license. With that exception, no new Compact facilities are proposed. This fluid, uncertain situation has inspired national level rulemaking initiatives and policy studies, as well as alternative disposal practices for certain low-activity materials.

Electronic sensors used in automotive and industrial applications have an increasing need for accuracy. To improve accuracy and reduce cost, electronic temperature compensation is often used. This paper presents a compensation algorithm that reduces die area by implementing a Pade Approximant to a curve using integer arithmetic. Sensors using this algorithm have achieved better than 0.5% accuracy over a temperature range from -40C to 130C.