Aries Design Automation (United States)

We study the efficient formal verification of polymorphic heterogeneous multi-core architectures, such as Bahurupi, and also present insights on how to design such architectures at a high level of abstraction in order to facilitates their formal verification. To the best of our knowledge, this is the first work on formal verification of such architectures.

We present a method for automatic formal verification of Digital Signal Processors (DSPs) that have VLIW architecture and reconfigurable functional units optimized for accelerating Software Defined Radio (SDR) applications to be used for future space communications by NASA. The formal verification was done with the highly automatic method of Correspondence Checking by exploiting the property of Positive Equality that allows a dramatic simplification of the solution space and many orders of magnitude speedup. The formal verification of a complex reconfigurable DSP took approximately 10 minutes of CPU time on a single workstation, when using our industrial-strength tool flow.

We present techniques for design and formal verification of both safety and liveness of pipelined/superscalar/VLIW processors with built-in mechanisms for soft-error tolerance. The formal verification is done with the highly automatic method of Correspondence Checking by exploiting the property of Positive Equality and efficient translations of the correctness conditions to equivalent Boolean formulas that are evaluated with SAT solvers. Soft errors are caused by radiation and cross talk between devices or wires on the chip, and will become increasingly frequent with the decreasing transistor sizes in future technologies. Soft errors can cause catastrophic failures in safety-critical applications, such as space, avionics, weapons systems, automotive, and medical devices. Thus, the need to design and efficiently formally verify pipelined microprocessors with mechanisms for soft-error tolerance.

With the number of processor cores in modern CPUs growing exponentially, it is expected that CPUs will have on the order of a hundred cores in the next 5 - 7 years. Thus, the need to implement parallel SMT decision procedures to utilize the increasing number of cores. We study a method to design independent strategies for a portfolio of parallel independent strategies in an SMT decision procedure for the logic of Equality with Uninterpreted Functions and Memories (EUFM). Particularly, our goal is to complement the previously used relative encoding (also called e <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ij</sub> encoding) and logarithmic encoding of equations by exploiting hierarchical encodings of equations. Hierarchical encodings can have a wide variety of structures, where each level of the hierarchy uses a different simple encoding, and thus the potential for many possible translations to SAT with such encodings. Hierarchical encodings produced a speedup of at least an order of magnitude for an out-of-order superscalar processor with issue/retire width of 14 instructions per clock cycle, such that the speedup increases with the complexity of the microprocessor under formal verification.

During the last eight years, tremendous progress was made in the field of Boolean Satisfiability (SAT). Now SAT solvers are 4 to 5 orders of magnitude faster, and can solve formulas that are 4 to 5 orders of magnitude bigger. SAT is the enabling technology for formal verification-the mathematical proof of correctness of computer systems. Statistics from industrial circuit designs indicate that up to 90% of the engineering effort is spent on verification, which increasingly becomes the bottleneck in developing new products. Formal verification, gaining wider acceptance in industry, has the potential to significantly reduce the design time, while also guaranteeing complete correctness and avoiding costly design bugs that can easily drive a company bankrupt. The seven regular papers and two research notes in this special volume present exciting work on applying SAT to formal verification and related domains.