BBK Electronics (China)

In order to improve the dispatch autonomy and localization control level of smart grid in complex operation environment, a domestic chip dispatch architecture based on edge collaboration is constructed, taking RISC-V architecture SoC and FPGA collaboration unit as the core, integrating the lightweight protocol stack, distributed collaboration mechanism, and edge-cloud scheduling strategy, and researching the optimization of multi-node scheduling and link adaptive mechanism. The system design covers key modules such as hardware architecture, communication protocols, state synchronization and scheduling security control, and has been validated in grid multi-source sensing and load prediction scenarios. It is analyzed that the architecture maintains the task response delay below 480ms and the scheduling stability fluctuation within $\pm 60 \mathrm{~ms}$ under high load conditions, and has good elasticity and robustness.

Abstract In this paper, an LED (Light-Emitting Diode) screen number detection method is proposed to guide the autonomous navigation of UAV (Unmanned Aerial Vehicle) for further task implementation. Aiming at the LED module identification in the task of detecting bright and dark lines on the LED screens, an improved YOLOv5 object detection algorithm has been developed with a series of operations, i.e., the backbone network, activation function, optimization strategy and post-processing screening prediction box. The LED dataset is designed, along with data augmentation so as to achieve a high detection accuracy of the trained detection model in too strong or too dark light complex scenes. The trained model can be transplanted to the Android platform, which provides support for subsequent UAV automatic navigation and portable screen calibration. With extremely high detection accuracy (0.843 mAP@0.5), the detection speed of the proposed model is also quite fast, achieving almost real-time performance (85 FPS).KeywordsLED modulesNumber detectionScreen calibrationYOLOv5

We report a strategy feasible for improving the internal gettering (IG) capability of iron (Fe) for n/n+ epitaxial silicon wafers using the heavily arsenic (As)-doped Czochralski (CZ) silicon wafers as the substrates. The n/n+ epitaxial silicon wafers were subjected to the two-step anneal of 650 °C/16 h + 1000 °C/16 h following the rapid thermal processing (RTP) at 1250 °C in argon (Ar) or nitrogen (N2) atmosphere. It is found that the prior RTP in N2 atmosphere exhibits much stronger enhancement effect on oxygen precipitation (OP) in the substrates than that in Ar atmosphere, thereby leading to a better IG capability of Fe contamination on the epitaxial wafer. In comparison with the RTP in Ar atmosphere, the one in N2 atmosphere injects not only vacancies but also nitrogen atoms of high concentration into the heavily As-doped silicon substrate. The co-action of vacancy and nitrogen leads to the enhanced OP in the substrate and therefore the better IG capability for the n/n+ epitaxial silicon wafer.

Multi-wire saw becomes the dominant method in slicing the hard brittle material into wafers. In this process, saw wire is the critical consumable and the dominant component of the wafer’s slicing cost. However, unreasonable process parameters lead to the fact that the saw wire was not fully used. This enormously increases the wire cost. For this reason, the constant wire wear loss model is presented by taking the free abrasive wire sawing as an example. This model takes the various cutting conditions into account and ensures the whole wire wear loss to reach the preset reasonable value. Firstly, a hypothesis that there is a mapping relation between the wire wear loss and the wire slicing area during the wire lifetime is built. According to this hypothesis, the wire allowed wear loss can be transformed into wire allowed slicing area. Secondly, the calculation method is deduced based on the model. The function relation is obtained between the wire feedback ratio and the actual slicing conditions under the constraint condition of the preset wire wear allowed loss. This rational feedback ratio of wire is obtained based on the actual process parameters. Thirdly, experiments are carried out. The results indicate that the relation between wire wear loss and wire slicing area is linear under the condition of the experiments and the wire consumption is reduced obviously. Meanwhile, wafers’ quality meets the requirements. This method can effectively save saw wire cost, referring to slicing other hard brittle materials by multi-wire saw.

Ni-P eutectic alloy film as an insert metal is successfully applied in joining clad pipes, and continuous electroplating technology was examined to plate Ni-P alloy on long metal foil for this application. Watts baths to which phosphorus acid had been added were found to be stable for continuous plating.Film composition can be easily maintained by using a soluble Ni anode and adding phosphorous acid.