Cirrus Logic (United Kingdom)

This paper presents a novel Capacitance to Digital Converter (CDC) for ultra-low power microphone-based auscultation. The proposed CDC utilizes a continuous-time Capacitance to Voltage Converter (CVC) inside a delta-sigma (ΔΣ) modulator to perform the Delta operation. The multi-bit feedback in the embedded CVC with a capacitive DAC reduces the voltage swing at its output, which permits a larger capacitive signal gain and relaxes the noise requirements. The multi-bit feedback also allows a larger signal swing at the CVC output, and improves the dynamic range. The proposed CDC was fabricated in 0.18 μm CMOS technology and was measured with a commercial capacitive sensor. Measurement results demonstrate that the proposed CDC consumes only 6.3 nJ while achieving 13-bit resolution. This corresponds to a FoM of 0.84 pJ/conversion-step.

A fully on-chip, fast load transient linear voltage regulator (LVR) based on sub-unity gain positive feedback loop utilizing a current subtractor loop and a transient enhancement loop is presented. Current subtractor loop is intended to improve DC load regulation and reduces quiescent current requirement of the LVR while transient enhancement loop provides better load transient performance. The LVR is implemented in 28FDSOI and generates 1.05V output from 1.3-1.98V primary input while using another 2.5-3.6V supply to power regulation loop. Load transient measurement results show that output exhibits a drop of only 65mV without any undershoot or overshoot for fast changing load current step of 75mA in 60ns and is stable with a wide range of capacitive loads from 100pF to 1μF. The LVR achieves an FOM of 0.29 along with wide band power supply rejection of -22dB@100MHz and supports convenient pass transistor distribution across the chip for uniform thermal dissipation.

During the last two decades, wireless communication has been revolutionized by near-capacity error-correcting codes (ECCs), such as turbo codes (TCs), which offer a lower bit error ratio (BER) than their predecessors, without requiring an increased transmission energy consumption (EC). Hence, TCs have found widespread employment in spectrum-constrained wireless communication applications, such as cellular telephony, wireless local area network, and broadcast systems. Recently, however, TCs have also been considered for energy-constrained wireless communication applications, such as wireless sensor networks and the ‘Internet of Things.’ In these applications, TCs may also be employed for reducing the required transmission EC, instead of improving the BER. However, TCs have relatively high computational complexities, and hence, the associated signal-processing-related ECs are not insignificant. Therefore, when parameterizing TCs for employment in energy-constrained applications, both the processing EC and the transmission EC must be jointly considered. In this tutorial, we investigate holistic design methodologies conceived for this purpose. We commence by introducing turbo coding in detail, highlighting the various parameters of TCs and characterizing their impact on the encoded bit rate, on the radio frequency bandwidth requirement, on the transmission EC and on the BER. Following this, energy-efficient TC decoder application-specific integrated circuit (ASIC) architecture designs are exemplified, and the processing EC is characterized as a function of the TC parameters. Finally, the TC parameters are selected in order to minimize the sum of the processing EC and the transmission EC.

Short-vector SIMD and DSP instructions are popular extensions to common Isas. These extensions deliver excellent performance and compact code for some compute-intensive applications, but they require specialised compiler support. To enable the programmer to explicitly request the use of such an instruction, many C compilers provide platform-specific intrinsic functions, whose implementation is handled specially by the compiler. The use of such intrinsics, however, inevitably results in non-portable code. In this paper we develop a novel methodology for retargeting such non-portable code, which maps intrinsics from one platform to another, taking advantage of similar intrinsics on the target platform. We employ a description language to specify the signature and semantics of intrinsics and perform graph-based pattern matching and high-level code transformations to derive optimised implementations exploiting the target's intrinsics, wherever possible. We demonstrate the effectiveness of our new methodology, implemented in the FREE RIDER tool, by automatically retargeting benchmarks derived from OpenCV samples and a complex embedded application optimised to run on an Arm Cortex-M4 to an Intel Edison module with Sse4.2 instructions. We achieve a speedup of up to 3.73 over a plain C baseline, and on average 96.0% of the speedup of manually ported and optimised versions of the benchmarks.