Cisco Systems (Israel)

Current network processors (NPs) increasingly deal with packets with heterogeneous processing times. As a consequence, packets that require many processing cycles can significantly delay low-latency traffic, because the common approach in today's NPs is to employ run-to-completion processing. These difficulties have led to the emergence of the Multipass NP architecture, where after a processing cycle ends, all processed packets are recycled into the buffer and re-compete for processing resources. In this work we provide a model that captures many of the characteristics of this architecture, and consider several scheduling and buffer management algorithms that are specially designed to optimize the performance of multipass network processors. In particular, we provide analytical guarantees for the throughput performance of our algorithms. We further conduct a comprehensive simulation study that validates our results.

We develop a simple analytical model that estimates when router bypass by OTN is cost effective. We use realistic metrics from large IP networks to calibrate the model and derive the required router/crossconnect cost ratio for breakeven.

This paper explores the power of failure detectors in read write shared memory systems with n processes whose names are drawn from the set {1...m}, m>=2n-1. We do so by making an additional assumption, name obliviousness, on top of the three failure detector assumptions introduced by ZieliDski. We present name non-oblivious failure detectors that are strong enough to wait-free solve the Symmetry Breaking (SB) problem, but not enough to solve the (n-1)-Set Consensus problem. Furthermore a family of weakest such failure detectors is presented. On the other hand we show that any non trivial name oblivious failure detector can wait-free solve (n-1)-Set Consensus, by introducing a simple extension to anti-Omega, the Loose-anti-Omega failure detector, and proving that it is the weakest failure detector that conforms to the four assumptions above.

The buffered crossbar switch architecture has recently gained considerable research attention. In such a switch, besides normal input and output queues, a small buffer is associated with each crosspoint. Due to the introduction of crossbar buffers, output and input contention is eliminated, and the scheduling process is greatly simplified. We analyze the performance of switch policies by means of competitive analysis, where a uniform guarantee is provided for all traffic patterns. The goal of the switch policy is to maximize the weighted throughput of the switch, that is the total value of packets sent out of the switch. For the case of unit value packets (Best Effort), we present a simple greedy switch policy that is 4-competitive. For the case of variable value packets, we consider the Priority Queueing (PQ) mechanism, which provides better Quality of Service (QoS) guarantees by decreasing the delay of real-time traffic. We propose a preemptive greedy switch policy that achieves a competitve ratio of 18. Our results hold for any value of the switch fabric speedup. Moreover, the presented policies incur low overhead and are amenable to efficient hardware implementation at wire speed. To the best of our knowledge, this is the first work on competitive analysis for the buffered crossbar switch architecture.

In all stages of an electro-optics system's life, development, production, and periodic maintenance, a large amount of manpower and time is devoted to testing. Each subsystem separately as well as the system as a whole are tested by a PC controlled test system, which consists of hardware for creation of the appropriate stimuli, and software for tests management and control. A very considerable portion of this manpower and time is devoted by the system manufacturer to configure the test routines, to manually input certain parameter values of the Unit Under Test (UUT) at predefined test nodes, and to reconfigure these routines from time to time, as the needs change during the system's life time. CI has developed the CTE (CI Test Executive), a software package which is a breakthrough in saving manpower and time devoted to electro-optics system testing. The new concept is based on: 1. The CTE can communicate directly with any UUT able to communicate with the outside world through a known protocol, to automatically set the UUT parameters before testing, 2. The user can more easily reconfigure the communication with the UUT through a provided special Excel file, without the help of the test system manufacturer, 3. The interface screen is automatically reconfigured every time the Excel file is changed to build the new test routine, 4. The CTE can simulate the test system stimuli with error injection capability, and simultaneously monitor communication and other hardware functions, 5. Test verification signals are provided on-line for the convenience and time saving of the test operator.

Enterprise software development typically involves cooperation among multiple entities. In a cross-platform software development environment, developers can categorize the source code of products into platform specific and platform generic components, so that common features can be deployed seamlessly across platforms. As the complexity of component and source code inter-dependency increases, build breakages occur more frequently, and the lack of an efficient detection mechanism often results in slow response with higher costs. We present a successful cost-effective method to automatically detect and identify such breakages. We deployed a centralized code validation and policing tool, and the results prove its effectiveness as an important quality assurance component in the software development process.

An IR target simulating projector system may sometimes require zooming lenses to simulate continuously the target's increasing size as a missile closes the range. In addition, special opto-mechanical layouts may sometimes be needed to allow cascaded action of two or more zooms to increase the zooming range, or to present the missile simultaneously two or more spectral regions. The zooms in these systems may differ in some important characteristics from the more conventional types: (1) The maximum speed and acceleration of their moving parts, as required by the dynamics of the missile-target approach scenario, are to be limited by the performance of commercially available stages carrying those parts, and (2) the motion control system must assure strict adherence to the 'zoom function' (relative position of the zoom's moving parts) to avoid defocusing during the zooming phase. In this paper we describe the implications of complying with these requirements on implementations actually designed and executed.

A few years ago, a microlithographic deposition process on infrared-transmitting substrates was developed in order to produce realistic infrared scenes for FLIR testing. In recent months, the performance of this product, named Thermoscene, has been improved by improving the control over the production process. The two main results are: (1) An increase in the number of simulated grey levels from 15 to 290, without reduction of the total number of pixels. (2) A decrease in imperfections, such as unwanted holes in the mesh deposition, to almost zero. The Thermoscene is useful as a component of infrared simulators, to project realistic infrared scenes through collimating optics to a FLIR, missile seeker, etc., for testing purposes.