ELAN Microelectronics (Taiwan)

Deep Trench Isolation (DTI) is a specialized isolation technique employed in the BCD process to mitigate latch-up issues. Unlike junction isolation, which was typically implemented by guard rings, the DTI offers a significant reduction in layout area due to its physical isolation capabilities. This study delves into the impact of DTI on latch-up immunity between 100-V LDMOS in the I/O circuits and the additional guard ring between the 100-V I/O circuits and 5- V internal circuits. The results of this study will be benefit to the high-voltage IC products, that drawn with reduced layout spacing but having high latch-up immunity.

Designing a high-efficiency and high-quality expressive network architecture has always been the most important research topic in the field of deep learning. Most of today's network design strategies focus on how to integrate features extracted from different layers, and how to design computing units to effectively extract these features, thereby enhancing the expressiveness of the network. This paper proposes a new network design strategy, i.e., to design the network architecture based on gradient path analysis. On the whole, most of today's mainstream network design strategies are based on feed forward path, that is, the network architecture is designed based on the data path. In this paper, we hope to enhance the expressive ability of the trained model by improving the network learning ability. Due to the mechanism driving the network parameter learning is the backward propagation algorithm, we design network design strategies based on back propagation path. We propose the gradient path design strategies for the layer-level, the stage-level, and the network-level, and the design strategies are proved to be superior and feasible from theoretical analysis and experiments.

d-glutamate, which is involved in N-methyl-d-aspartate receptor modulation, may be associated with cognitive ageing. This study aimed to use peripheral plasma d-glutamate levels to differentiate patients with mild cognitive impairment (MCI) and Alzheimer's disease (AD) from healthy individuals and to evaluate its prediction ability using machine learning. Overall, 31 healthy controls, 21 patients with MCI and 133 patients with AD were recruited. Serum d-glutamate levels were measured using high-performance liquid chromatography (HPLC). Cognitive deficit severity was assessed using the Clinical Dementia Rating scale and the Mini-Mental Status Examination (MMSE). We employed four machine learning algorithms (support vector machine, logistic regression, random forest and naïve Bayes) to build an optimal predictive model to distinguish patients with MCI or AD from healthy controls. The MCI and AD groups had lower plasma d-glutamate levels (1097.79 ± 283.99 and 785.10 ± 720.06 ng/mL, respectively) compared to healthy controls (1620.08 ± 548.80 ng/mL). The naïve Bayes model and random forest model appeared to be the best models for determining MCI and AD susceptibility, respectively (area under the receiver operating characteristic curve: 0.8207 and 0.7900; sensitivity: 0.8438 and 0.6997; and specificity: 0.8158 and 0.9188, respectively). The total MMSE score was positively correlated with d-glutamate levels (r = 0.368, p < 0.001). Multivariate regression analysis indicated that d-glutamate levels were significantly associated with the total MMSE score (B = 0.003, 95% confidence interval 0.002-0.005, p < 0.001). Peripheral plasma d-glutamate levels were associated with cognitive impairment and may therefore be a suitable peripheral biomarker for detecting MCI and AD. Rapid and cost-effective HPLC for biomarkers and machine learning algorithms may assist physicians in diagnosing MCI and AD in outpatient clinics.

Silicidation has been reported to result in substantial negative impact on the electrostatic discharge (ESD) robustness of MOS field-effect transistors. Although silicide blocking (SB) is a useful method to alleviate ESD degradation from silicidation, it requires additional mask and process steps to somehow increase the fabrication cost. In this paper, two new ballasting layout schemes to effectively improve the ESD robustness of input/output (I/O) buffers with fully silicided NMOS and PMOS transistors have been proposed. Ballasting technique in layout is a cost-effective method to enhance the ESD robustness of fully silicided devices. Experimental results from real IC products have confirmed that the new ballasting layout schemes can successfully increase the HBM ESD robustness of fully silicided I/O buffers from the original 1.5 kV to over 6 kV without using the additional SB mask.

An ESD protection structure of HVPSCR embedded into the high-voltage PMOS device is proposed to greatly improve ESD robustness of the vacuum-fluorescent-display (VFD) driver IC for automotive electronics applications. By only adding the additional N+ diffusion into the drain region of HVPMOS, the It2 of output cell has been greatly improved form 0.07A to be greater than 6A within the almost same layout area. Such an ESD-enhanced VFD driver IC has been in mass production for automotive applications in car to sustain HBM ESD stress of up to 8kV.

Abs trnc t In this work we use noise measurement on Polyemitter BJT to ,determine the base series resistance for low d.c bias voltages. The base series resistance consists of contact resistance and bulk resistance.This method is based on the resistance thermal noise theory and Hybrid?r small signal model. The measured data show that the base series resistance decreases as the base-emitter voltage increases. The base series resistance Rb is very important for the performance of bipolar transistor and circuits design. It is strongly dependent on the device geometry,doping concentration and the applied bias condition. There are several simulation[l] and measurement[Z]-[5] methods to determine the value of Rb. The experimental measurement includes a.c. , d.c. ,special structure and noise methods[2]'[5]. The a.c method is operated at low current, so that the measured Rb is applied for use to the low bias condition typically VBE s 0.4V. The d.c. method is operated at high current region, the value of Rb is only applied to the very high bias voltage condition typically VBE 2 0.W. In this paper,the noise measurement method is used to determine the Rb with the BJT operated at the region 0.6V .I; VBE 5 0.8V. Section I1 describes the model and method used to determine base series resistance. The experimental details is discussed in section 111.