Edacentrum

For a speed-up of analog design cycles to keep up with the continuously decreasing time to market, iterative design refinement and redesigns are more than ever regarded as showstoppers. To deal with this issue, referred to as design and verification gap, the development of a continuous and consistent verification is mandatory. In digital design, formal verification methods are considered as a key technology for efficient design flows. However, industrial availability of formal methods for analog circuit verification is still negligible despite a growing need. In recent years, research institutions have made considerable advances in the area of formal verification of analog circuits. This paper presents a selection of four recent approaches in analog verification that cover a broad scope of verification philosophies.

This paper describes ongoing research in the field of quantitative productivity measurement in IC Design and simulation of different scenarios as decision support. Five topics out of this research field allow an insight in the preparation of real design flows for productivity measurement and how these measurements are used for analysis, simulation and optimization of design flows. This paper starts with an introduction in section 1 of the PRODUKTIV+ project in which most of the research has been done. The modeling of projects and extraction of the important indicators complexity and quality is explained in sections 2 and 3. In section 4 Synopsys as an EDA vendor from outside of PRODUKTIV+ adds its view on productivity measurement. Section 5 contributes to the modeling of a verification process for productivity simulations. Section 6 explains an optimization process for a microprocessor design flow under productivity considerations.Most of this work has been carried out in the PRODUKTIV+ project (label 01 M 3077) that is partly funded by the German government [17].