Ellemedia Technologies (Greece)

This paper describes a novel approach for the design of a time domain equalizer for a Discrete Multi Tone (DMT) Digital Subscriber Loop (DSL) modem. The key role of the equalizer is to act upon the equivalent digital channel impulse response at the receiving end to yield a combined impulse response with a linear phase characteristic. Using two-port channel models from the ANSI VDSL standard [1] it is shown how group delay characteristics of typical channels can be modeled by small order polynomials that fall into one of the following categories; all-zero mixed phase, all-pole mixed phase, ARMA minimum phase, and finally ARMA maximum phase systems. A discussion follows to suggest a suitable algorithm based on Prony's method for finding appropriate minimum phase channel models which can be inverted to give equalizer blocks.

Enhancements and innovations in microelectronics and multimedia processing technologies have made new services available and generaied new video compression standards. H.264 is expected io replace the use of MPEG-1.2,4, H.323 in digital video systems. However, the complete migration is expected to take several years given the wide scale use of its predecessors. Moreover, applications like home surveillance and video teleconference require eflcient, adaptive encoding and advanced techniques e.g. focusing on Regions of Interest (ROQ. This creates the need for transcoding technologies and platfbrms. The high complex+ of real-time transcoding can be overcome by utilizing a HW re-con$gurable signal-processing platform. In this paper we discuss the issues in transcoding and propose a HW programmable piaQ6m that can be used for re- conjigurable video transcoding.

Log-domain wave filters that simulate the passive LC ladder prototype filters are introduced in this paper. The proposed circuits are constructed from the wave equivalents of the reactive elements corresponding to those in the prototype circuit. The wave equivalent circuits are obtained by using a novel log-domain wave port terminator. The wave equivalent of a capacitor in a shunt branch was chosen as an elementary building block for creating high-order filters. The wave equivalent circuits of all other reactive elements in a shunt or in a series-branch connection can be readily obtained using the elementary building block plus some inverters. This way the derived high-order filter configurations are modular. A design example of a third-order elliptic low-pass filter is given, and the performance of the filter was verified by simulation.

As it has already been proved, link layer compression is very effective when used in packet networks. We believe that such compression schemes will also be widely used in the future networks, just as low level high-speed encryption is used today. In this paper we present the performance against complexity tradeoffs of such compressor/decompressor devices with reference to probably the only known. system that can work at multi-gigabit networks. The displayed experiment results show that the compression algorithm this system implements is very effective when used in real networks. It is also claimed that compression devices with throughput ranging from several megabits to tens of Gigabits can be efficiently implemented based on the reference architecture.

Digital signal processing development and testing can considerably benefit by utilising an embedded, fully programmable platform architecture, independent from the particular, under development, algorithmic set. In this paper we present a fully programmable platform that integrates a mixture of digital signal processor (DSP) cores and field programmable gate arrays (FPGAs) along with a control and management microprocessor. This system may offer an ideal platform for bridging the gap between simulations and laboratory tests/field trials. Moreover, such a platform can be considerably helpful not only on digital systems development, but also as an educational platform for courses like digital signal processing, embedded microprocessors programming and VHDL programming.

In order to address the challenge of providing quality of service guarantees in today's network processing systems, the use of efficient scheduling algorithms is required. The efficiency of a scheduler is determined by several factors including its fairness, capability to operate at high speeds, as well as the resources required for its implementation. We present an architecture to support fair scheduling (gigabit FS) considering variable length packets (i. e. for packet forwarding/switching networks) over gigabit links. This high speed scheduler is designed to manage 32 K flows based on an algorithm that yields efficient implementation in hardware by avoiding the complexity of computing the system virtual time function that many packet fair queueing (PFQ) algorithms have proposed. Further, we demonstrate the critical factors in designing an effective scheduling engine at gigabit rates and we present several enhancements together with their associated cost.

Two of the main bottlenecks when designing a network embedded system are very often the memory bandwidth and its capacity. This is mainly due to the extremely high speed of the state-of-the-art network links and to the fact that in order to support advanced quality of service (QoS), per-flow queueing is desirable. In this paper we describe the architecture of a memory manager that can provide up to 10Gbs of aggregate throughput while handling 512K queues. The presented system supports a complete instruction set and thus we believe it can be used as a hardware component in any suitable embedded system, particularly network SoCs that implement per flow queuing. When designing this scheme several optimisation techniques have been evaluated and the most cost and performance effective ones used. These techniques minimize both the memory bandwidth and the memory capacity needed, which is considered a main advantage of the proposed scheme. The proposed architecture uses a simple DRAM for data storage and a typical SRAM for keeping data structures-pointers, therefore minimising the system's cost. The device has been fabricated within a novel programmable network processor designed for efficient protocol processing in high speed networking applications. It consists of 155K Gates and occupies 5.23 mm in UMC 0.18υ CMOS.

To meet the demand for higher performance, flexibility, and economy in today's state-of-the-art networks, great emphasis is placed on unconventional hardware architectures of network processors. This paper analyzes the problem of processor internal resource and traffic management and proposes a programmable scheduler architecture implemented in a novel protocol processor that deals with the above problems in an integrated way. We briefly outline the architecture of the protocol processor and we support that the innovative scheduling scheme integrated in PRO3 is, in general, crucial for network Systems-on-Chip since it makes it feasible to use scheduler's architecture are discussed that lead to efficient integration of the component to different network processor architectures at a similar cost. Its beneficial features are easy hardware implementation, low memory bandwidth requirements and high flexibility so as to support multiple service disciplines in a programmable way, thousands of flows and even perform different scheduling tasks.

New interactive multimedia services have increased the urgent requirement for more bandwidth and turn broadband wireless technology as one of the most competitive solutions for the last mile problem. This paper presents an adaptive transport protocol design and evaluation for a multicarrier point-to-multipoint outdoor broadband wireless access system, in the 5.8 GHz and 10.5 GHz frequency bands. With minimal overhead, the protocol is able to support multiple terminals and services that range from video broadcasting to full symmetric traffic. Moreover, adaptive modulation and coding schemes can be applied per terminal per time frame, in either the downlink or the uplink direction. In the proposed system various innovative techniques are used for efficient utilization of the available bandwidth. Finally, the protocol gain is evaluated.

The evolution of wireless networks has motivated the expansion of the static business environment to a mobile and wireless one. However, current and forthcoming wireless technologies are characterized by different attributes, regarding coverage area, offered bandwidth and delay. The transparent conjunction of various wireless technologies into a single mobile terminal can further boost the wireless explosion. This paper presents the Wireless Convergence Architecture (WCA) that incorporates different wireless interfaces under the same mobile terminal. Depending on the location and the availability of the underlying wireless network, automatic and seamless switching is performed to the most appropriate wireless network interface. Special care is taken to maintain continuous connectivity at the transport layer (TCP). WCA introduces software components both at the terminal and network side. A specific implementation is presented, based on two complementary wireless technologies --- in terms of coverage area --- an IEEE 802.11-compliant in the short local and a GSM in the wide area. To demonstrate the operational correctness of the architecture, experiments were performed using standard and proprietary networking applications.