Eutecus (United States)

This paper presents an architecture for the implementation of vision chips in 3-D integration technologies. This architecture employs the multi-functional pixel concept to achieve full parallel processing of the information and hence high processing speed. The top layer includes an array of optical sensors which are parallel-connected to the second layer, consisting of an array of mixed-signal read-out and pre-processing cells. Multiplexing is employed so that each mixedsignal cell handles several optical sensors. The two remaining layer are respectively a memory (used to store different multi-scale images obtained at the mixed-signal layer) and an array of digital processors. A prototype of this architecture has been implemented in a FDSOI CMOS-3D technology with Through-Silicon-Vias of 5μm x 5μm pitch. © 2010 Copyright SPIE - The International Society for Optical Engineering.

In this chapter, a generic multi-fovea video processing architecture is presented, which supports a broad class of algorithms designed for real-time motion detection in moving platform surveillance. The various processing stages of these algorithms can be decomposed into three classes: computationally expensive calculations can be focused onto multiple foveal regions that are selected by a preprocessing step running on a highly parallel topological array and leaving only the nontopological (typically vector-matrix) computations to be executed on serial processing elements. The multi-fovea framework used in this chapter is a generalized hardware architecture enabling an efficient partitioning and mapping of different algorithms with enough flexibility to achieve good compromise in the design tradeoff between computational complexity versus output quality. We introduce and compare several variants of four different classes of state-of-the-art algorithms in the field of independent motion analysis and detection. On the basis of the analysis, we propose a new algorithm called the Elastic Grid Multi-Fovea Detector characterized by moderate hardware complexity while maintaining competitive detection quality.

Abstract Mixed‐signal cellular visual microprocessor architecture with digital processors is described. An Application Specific Integrated Circuit (ASIC) implementation is also demonstrated. The architecture is composed of a regular sensor readout circuit array, prepared for 3D face‐to‐face‐type integration, and one or several cascaded array of mainly identical (single instruction multiple data, SIMD) processing elements. The individual array elements were derived from the same general Hardware Description Language (HDL) description and could be of different sizes, aspect ratio, and computing resources. Copyright © 2008 John Wiley & Sons, Ltd.

Abstract A bit‐sliced digital implementation method of the cellular sensor‐computer is proposed. The proposed sensor‐computer architecture is analysed, and an implementation example is introduced. The analogue and the digital implementation methods are compared. It is found that on or below 0.18 µm technology the digital implementation of the cellular sensor‐computer is a viable alternative to the analogue versions in general‐purpose designs. Copyright © 2006 John Wiley & Sons, Ltd.