Fraunhofer Institute for Integrated Systems and Device Technology

PERC solar cells based on Gallium p-type doping were treated at elevated temperatures in the range of 80…160°C and current injection. Current injection is conducted in a current-induced degradation (CID) setup in the dark, measuring voltage while applying a current at 0.06, 0.53 and 1.0 times the short-circuit current – ranging from maximum power point to open-circuit injection conditions. The results of the CID treatment show no significant light and elevated temperature induced degradation (LeTID) behaviour for these Ga-doped PERC cells. PERC cells treated at temperatures above 110°C show an increase in relative voltage during CID starting the earliest at a measurement time of 50 hours. It was found that the voltage increase could be related to increased contact resistance between the front silver metallization and the phosphourus emitter as indicated by comparing electroluminescence imaging before and after CID treatment and confirmed by transfer length method measurements. These measurements on a cut-out stripe showed an increase in contact resistivity and a lateral intensity variation as visible in the post electroluminescence image.

Abstract In this work, epilayers of n-3C-SiC on Si were investigated using Deep Level Transient Spectroscopy (DLTS). The layer structure allowed the investigation of electrically active defects in the n type region of 3C-SiC. By comparison with theoretical calculations based on density functional theory (DFT) supercells in combination with local moment counter charge (LMCC) from the literature, the observed DLTS peaks could be assigned to intrinsic defects, more specifically different clusters of vacancies and silicon interstials. The defects may be formed due to the different lattice constants of 3C-SiC and Si, similarly to the dislocations and voids previously observed in TEM studies. Our studies suggest that the DLTS peak observed close to 260 K originates from overlapping two intrinsic defects containing a single positively charged carbon vacancy and a single positively charged silicon interstitial.

In this work, a method is presented to form structured low-ohmic p-type contacts on Al-implanted 4H-SiC by laser annealing. A metal layer sequence for p-type contacts suitable for UV laser treatment was developed. Furthermore, a method to protect thermosensitive layers from damages by laser treatment is presented. By structuring the top metallization layer, it is possible to use the metal stack as a self-aligned mask. That makes it possible to laser the entire surface of the wafer, whereby thermosensitive layers are protected from damages by laser annealing by utilizing the optical properties of the individual metal layers. To evaluate the method, TLM structures were electrically characterized. TLM structures were electrically characterized successfully demonstrating the feasibility of the presented approach.

Engineered SiC wafers with a thin 4H-SiC layer bonded on a polycrystalline carrier substrate for the application as substrate in epitaxy are investigated. Epitaxial layers grown on such substrates in 150 mm and 200 mm diameter are compared to those on state-of-the-art conventional substrates from different vendors. The performance of the engineered wafers is judged by doping and thickness uniformities as well as the number and statistics of killer defects in the epitaxial layer.

Because of their advantageous properties, silicon nanowires are considered as basic structures in many concepts of future electron devices. With the high energy density induced during manufacturing but also during operation, heat dissipation is a crucial point for both. While heat transport along the nanowire axis has been investigated already intensively, we note that heat dissipation occurs predominantly in radial direction. In this work, we investigated heat conduction in radial direction by molecular dynamics simulations. The effective thermal conductance for the thermal transport in radial direction increases approximately linearly with the radius of the nanowires and, in contrast to the axial thermal transport in nanowires, is almost independent of nanowire length. A reduction of the thermal conductivity in silicon by a factor of 1.5–3.5 near the silicon-to-oxide interface for the heat flow in radial direction was found. This reduction of the thermal conductivity is a manifestation of the Kapitsa thermal resistance at the silicon-to-oxide interface. Numerical results from molecular dynamics simulations were compared to literature results and comprised to analytical models that enable the time-efficient calculation of heat dissipation which include the specifics of the thermal transport in radial direction in nanowires including the Kapitsa resistance, localized phonon modes at the interface and dependences on the nanowire dimensions.

We present a simplified manufacturing process, where flexible pressure sensors are produced employing a paste of graphene nano platelets in a polymer matrix, that is drop casted on a flexible polyimide sheet with an electrode pair. For that the influence of the amount of solvent and graphene and the type of the matrix material are investigated. The sensors were characterized by resistance measurements in dependence of the applied pressure. The results of manufacturing and characterization show a clear dependence of the sensitivity on the viscosity of the paste, rather than on the amount of graphene and the type of polymeric material. Knowing this, the operation range and the precision of the sensors can be customized to the application. Maximum sensitivities of 0.0023 to $0.000751 / \mathrm{KPa}$ could be achieved at a coefficient of determination of 0.99. The devices also proof precise results in a long-term stability test over 14 days.

A temperature sensor based on a diode-connected 4H-Silicon Carbide p-type metal oxide semiconductor field effect transistor is characterized in the temperature range between 14 K and 482 K and its performance has been analyzed. The study shows that the sensor characteristics are mainly affected by the threshold voltage, but an unusual reduction of the device current is shown for temperatures lower than 76 K, which limits the linearity of the sensor response. Indeed, two operating temperature ranges could be defined. The first one is in the range <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$ \text{76 K}\leq T \leq \text{175 K}$</tex-math></inline-formula>, showing a linearity of 0.991 in terms of coefficient of determination and a sensitivity of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$ \text{6.24 mV/K}$</tex-math></inline-formula> at a device current of 3.34 nA, instead the second range is for temperatures higher than 175 K with a linearity of 0.986 and a sensitivity of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$ \text{66.37 mV/K}$</tex-math></inline-formula> for a current of 263 nA. Moreover, the device is fully compatible with 4H-SiC CMOS technology making possible its use in integrated circuits.

Zero Overvoltage Switching (ZOS) is a method that enables transistors to perform turn-off transitions at maximum speed, thereby minimizing switching losses, while simultaneously preventing overvoltage oscillations despite the high switching speed. However, only discrete turn-off current values exist where ZOS is applicable. This paper presents novel techniques to broaden the operational area where ZOS can be utilized. This is accomplished with active control of resonant elements. The range of options for further turn-off currents where ZOS is applicable is outlined and evidenced by tests conducted on a prototype. This approach not only increases the versatility of ZOS but also improves its applicability in power electronic systems.

In this work, the temperature dependence of all relevant resistances of a 4H-SiC CMOS technology for hightemperature applications is investigated from room temperature up to 550 degrees C. This includes sheet resistances (Rsh) of differently doped regions, metallization layers (Ti/Pt and Ti/Pt/Ti layer stacks), and highly n-doped polycrystalline silicon as well as specific contact resistivity (rc) to highly n- and p-doped 4H-SiC obtained by N and Al implantation, respectively. Different test structures were used for comparison and consistency of the results. Positive temperature coefficients of resistance were observed for the metallization layers (2,700 ppm/K) and for highly n-doped polycrystalline silicon (1,360 ppm/K). Rsh and rc for highly n-doped 4H-SiC regions show only moderate variation with temperature whereas a rather strong decrease of Rsh and rc can be observed for highly p-doped 4H-SiC and of Rsh for moderately p-doped 4H-SiC from room temperature up to 200 degrees C which is mainly due to incomplete ionization of Al-doped regions. For implanted regions, modeled Rsh(T) data qualitatively confirm measured results.

This paper addresses the development and modeling of a novel negative-tone photoresist, the Multi-Trigger Resist (MTR), aimed at enhancing extreme ultraviolet (EUV) lithography. The primary objectives are to create a stochastic model of the photoresist process flow and to analyze the behavior of MTR under various conditions. The model incorporates statistical fluctuations in photon distribution, secondary electron generation, and molecular distribution within the photoresist. Calibration with experimental data demonstrates the model’s capability in predicting critical dimension (CD), line width roughness (LWR), and dose-to-size (DtS) metrics. Results indicate that higher MTR loading and quencher addition improve performance consistency. Further investigation into different exposure types, electron blur lengths, and photoresist absorbance coefficients reveals the intricate balance required for optimizing lithographic outcomes. The findings underscore the model’s utility in guiding the design of next-generation photoresists and highlight areas for future research, including the expansion of calibration datasets and the application to various lithographic features.