Gemalto (France)

The Internet of Things is taking hold in our everyday life. Regrettably, the security of IoT devices is often being overlooked. Among the vast array of security issues plaguing the emerging IoT, we decide to focus on access control, as privacy, trust, and other security properties cannot be achieved without controlled access. This article classifies IoT access control solutions from the literature according to their architecture (e.g., centralized, hierarchical, federated, distributed) and examines the suitability of each one for access control purposes. Our analysis concludes that important properties such as auditability and revocation are missing from many proposals while hierarchical and federated architectures are neglected by the community. Finally, we provide an architecture-based taxonomy and future research directions: a focus on hybrid architectures, usability, flexibility, privacy, and revocation schemes in serverless authorization.

Wireless cellular networks will help Distribution System Operators (DSOs) to achieve observability below the substation level, which is needed to ensure stable operation in the smart grid. Both existing and upcoming cellular technologies are considered as candidates for helping to enable the smart grid. In the present chapter, we present the main features of both the non‐3GPP technologies, IEEE 802.11ah, Sigfox, and LoRa, and the main features of past, current, and future 3GPP technologies, namely releases <12 (High rate), 12 – 14 (IoT extensions) and 15–16 (5G). Additionally, we present the challenges and possible solutions for ensuring end‐to‐end security in smart grid systems.

Recording the ownership of assets has historically constituted a cumbersome procedure requiring the intervention of third parties that cannot be freely chosen and take a hefty fee. Its high cost had this process reserved for valuable assets such as real estate, cars, jewelry or artwork. The system itself is also vulnerable to corruption as records can be manipulated by malicious actors. The blockchain presents a solution to both these issues.

This experimental study addresses the problem of assessing the digital security of System on Chip (SoC) against electromagnetic (EM) hardware attacks through their packages. With large and complex circuits such as SoC, finding the right location and the right time to examine attacks such as side channel analysis and fault injection is a real challenge. In addition, setting up properly the parameters of these attacks is time consuming. Through an application on a commercial SoC, this article presents an approach which from a side channel analysis results, performs a fault injection attack. This approach shows firstly, the potential time saved to determine the injection time parameter of the fault attack and secondly, it enables to analyze the duality between the emission fields and the areas where errors occur. Thus, a security test of the SoC against EM field is presented in this study.

Security risk management and mitigation are two of the most important items on several companies' agendas. In this scenario, software attacks pose a major threat to the reliable execution of services, thus bringing negative effects on businesses. This paper presents a formal model that allows the identification of all the attacks against the assets embedded in a software application. Our approach can be used to perform the identification of the threats that loom over the assets and help to determine the potential countermeasures, that is the protections to deploy for mitigating the risks. The proposed model uses a Knowledge Base to represent the software assets, the steps that can be executed to mount an attack and their relationships. Inference rules permit the automatic discovery of attack step combinations towards the compromised assets that are discovered using a backward programming methodology. This approach is very usable as the attack discovery is fully automatic, once the Knowledge Base is populated with the information regarding the application to protect. In addition, it has been proven highly efficient and exhaustive.

We propose in this paper to reuse the existing payment infrastructure to introduce a proof of transaction genuineness computed by a smart card chip. The idea is to divide the amount of the transaction into several sub-amounts, which added together give the total amount. The sub-amounts are function of a secret shared with the bank, which can verify that the split is correct, thus proving that the transaction is authentic. We provide here a description of the algorithm and its implementation in a .NET card.

We present a new construction of divisible e-cash that makes use of 1) a new generation method of the binary tree of keys; 2) a new way of using bounded accumulators. The transaction data sent to the merchant has a constant number of bits while spending a monetary value 2ℓ. Moreover, the spending protocol does not require complex zero-knowledge proofs of knowledge such as proofs about double discrete logarithms. We then propose the first strongly anonymous scheme with standard unforgeability requirement and realistic generation parameters while improving the efficiency of the spending phase.

The variable clock (VC) side-channel countermeasure consists in clocking a chip with an internal oscillator whose parameters (frequency, duty cycle, shape, etc.) vary randomly in time. In this paper, we use parametric deconvolution to process VC-power consumption curves. We also analyze experimental results in order to show its efficiency.

Today users are faced with a, wide variety of access methods to computational resources. These methods may include the use of different devices. In this paper we present a a new type of devices, called eGo (ego: latin root expressing “me”), capable of providing a uniform, flexible and secure way to access such services. Furthermore, these devices allows users to take ownership of services and other devices in a natural and transparent way: by touching them.

In this paper, we present Decim v2, a stream cipher hardware-oriented selected for the Phase 3 of the ECRYPT stream cipher project eSTREAM. As required by the initial call for hardware-oriented stream cipher contribution, Decim v2 manages 80-bit secret keys and 64-bit public initialization vectors. The design of Decim v2 combines two filtering mechanisms: a nonlinear Boolean filter over a LFSR, followed by an irregular decimation mechanism called the ABSG. Since designers have been invited to demonstrate flexibility of their design by proposing variants that take 128-bit keys, we also present a 128-bit security version of Decim called Decim-128.