GlobalFoundries (United Kingdom)

Plasma-induced damage (PID) is a major cause of yield loss in standard semiconductor fabrication, typically driven by plasma charging during dielectric or metal etching process. This kind of damage usually hits devices with gate dielectrics, where accumulated charge leads to dielectric breakdown. To prevent it, design rules based on metal-to-gate area ratios are applied. This study examines a less explored failure mode known as reverse antenna charging. Here, the damage doesn’t occur at the gate dielectric but within the back-end-of-line (BEOL) interconnects, away from the front-end-of-line (FEOL) devices. Phenomenon was first observed in product and then test structures were built for thick oxide gate dielectric devices through a common BEOL interconnect path strategy. Gates were routed through CA, M1, V1, M2, V2, and M3 layers, with failures observed at the M1-V1 levels for structures connected to thick gate devices when discharge paths were intentionally designed to be weak. Under these conditions, reverse charging effects were successfully isolated and reproduced, resulting in hard open failures. The results confirm that yield loss can still occur even when thick gate devices are designed according to existing antenna rule strategies. This points to a failure mechanism that current rules did not address. As a result, a need is identified for existing design strategies to be revised to account for reverse antenna charging and its impact on BEOL interconnect reliability.

This work presents a novel configurable hysteresis Schmitt trigger for Automotive Grade-1 General-Purpose InputOutput (GPIO) applications. The proposed circuit is designed using the GF 22FDX™ process technology. The Schmitt trigger thresholds, <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$V_{H}$</tex> and <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$V_{L}$</tex>, can be configured either through externally applied control voltages or via internally generated ones. The hysteresis range is adjustable from 300 mV up to 1.5 V, with the observed <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$V_{H}$</tex> and <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$V_{L}$</tex> values being 1.25-3.1 V and 0.3-1.0 V, respectively. This proposed circuit is compact, with an area measuring <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$29.54 \times 18.925 \mu \mathrm{m}^{2}$</tex>. The dynamic power consumed is <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$280 \mu W$</tex>, whereas the leakage power is <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$1.25 n W$</tex>.

In this work, we present the recent advancements in the industry-standard surface potential-based BSIM-SOI compact model, designed for state-of-the-art SOI devices. The model incorporates a surface potential-based core that helps in the accurate modeling of partially depleted (PD), fully depleted (FD), and dynamically depleted (DD) regions, maintaining the inherent symmetry of the device. Enabled by a robust surface potential coupling relation, the model is well-suited for system-on-chip (SoC) designs, covering analog, digital, and RF applications. Key improvements include an updated effective mobility model, independent body resistances for the primary FET and process-induced parasitic opposite-type-gate FETs, decoupling of core I-V and C-V models, and integration of low-frequency shot noise for floating-body structures. These enhancements significantly improve the model's accuracy in capturing real hardware data. Additionally, proposed speed optimizations enhance the model's efficiency, making it more suitable for high-performance simulations.

Boolean satisfiability (SAT) attacks have been proven to be highly effective against logic locking techniques that secure intellectual property (IP). Prior research has improved the output corruptibility and SAT attack resiliency of logic locking, but often results in large overheads, higher design effort, increased delay and area/energy consumption. This work presents FeSATLock- a novel ferroelectric FET (FeFET) lookup table (LUT) based energy efficient and secure logic locking technique exploring the FeFET tunable device characteristics leading to both steep-slope characteristics for energy efficient circuit design and hysteresis behavior for non-volatile (NV) memory design. A FeFET LUT based key gate architecture has been proposed for key management and obfuscating the original circuit. A complete logic locking framework is demonstrated utilizing the proposed FeFET LUT based key gates, and performance has been benchmarked with baseline 40nm Complementary Metal Oxide Semiconductor Static Random Access Memory (CMOS SRAM) LUT based design at <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${\mathrm{V}}_{\mathbf {DD}} =0.5$ </tex-math></inline-formula>V. Due to the steep slope characteristics, at an optimal ferroelectric layer thickness (<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${\mathrm{t}}_{\mathbf {fe}}$ </tex-math></inline-formula>), FeFET LUT key gate design achieves <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\sim 2.68\times $ </tex-math></inline-formula> lower energy consumption, and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\sim 6.01\times $ </tex-math></inline-formula> higher speed with ~23% reduction in transistor count, compared to the baseline CMOS SRAM based key gate designs. The proposed FeFET LUT based locked circuit with key gates demonstrate <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\sim 2.21\times $ </tex-math></inline-formula> reduction in energy consumption and ~4.75x improvement in circuit speed in comparison to baseline CMOS SRAM based locked designs. The proposed logic locking design methodology is further evaluated against SAT attack, robustness is compared with the existing XOR, MUX based techniques and demonstrate higher SAT attack resiliency.

In this article, we have compared the negative capacitance complementary FET (NC-CFET) from a devicecircuit perspective with the experimentally demonstrated CFET. NC-CFET could potentially offer additional advantages over conventional CFET, like enhancement in the sub-threshold behavior, reduction in threshold voltage variability, improvement in noise margin, low supply voltage, and high-speed operation, etc. The comparative study shows the improvement in the logic devices, as well as SRAM memory cell with the use of negative capacitance concept. Detailed circuit-level simulations have been used to analyze the performance gains with NC-CFET. Further, we have demonstrated multi layer NC-CFET with vertically stacked N/P channels for ON-current matching, symmetric inverter switching, and improved static noise margin (SNM) in SRAM.

Correction for ‘Aluminal speciation in the crystal nucleus: a mass spectral interpretation’ by Alan Stewart Hare, RSC Adv., 2016, 6, 86540–86559.