IQE (United States)

Quantum Dot Lasers are seeing a resurgence of interest as potential replacements for optical transceivers in energy efficient datacentres. Integration of QDLs onto Si photonics platforms enables low-cost mass production of datacom lasers by leveraging established CMOS foundry processing. Access to a 150mm GaAs based QDL enables any established GaAs manufacturer to enter the datacom sector. Wafer to wafer variation <3nm and within wafer variation < 0.25% at 1290 nm is typical for a multi wafer run. A p-down version enables with an RMS <0.5nm enables flip chip bonding of III-V materials. Data for QDs heterogeneously grown on a 300mm PIC shows positioning of a QD region within 80nm of the waveguide after 3um of epitaxy. Growth of QDLs on Ge will also be presented. This offers a path to 300mm but is best suited to a cost effective 200mm solution. Moreover, Ge substrates are CMOS compatible. Data will show similar PL characteristics to material grown on GaAs. In summary we will present data from a high volume QDL manufacturing platform that can meet the demands of substrate form factor, substrate material and upstream QDL process flow.

MBE and MOVPE growths of InP-based extended wavelength and GaSb-based IR emitter and detector structures have progressed to production mode. These photonics device structures are typically grown using large format, multi wafer MBE and MOCVD tools and on large diameter substrates (100 to 150 mm). In this work, material characterization data of advanced InP- and GaSb based epitaxial structures will be shown. Multi point measurements showing cross-wafer and cross-platen uniformity will also be shared. Finally, detailed analysis of run-to-run epiwafer data will be presented to demonstrate the manufacturability of our production epitaxial process for these advanced photonics device structures.

The Sb concentration profile in an nBn photodetector containing an InAs/InAsSb type-II superlattice is collected and analyzed using atom probe tomography. A 3D reconstruction comprises the full composition of 31 periods. The Sb concentration profile is evaluated for the entire 31 period stack, as well as each individual period using segregation models from Muraki and Wood. Trends in the asymmetric Sb profile show a consistent non-negligible Sb concentration in the InAs layers and a lower Sb concentration in the InAsSb with respect to the target concentration.

We recently evaluated the optical and electric characteristics of mid-wave photodetector (PD) diodes grown on high-index substrates. Preliminary results indicate that substrate orientation and surface polarity can modify PD parameters such as photoluminescence (PL), dark current (Jd), quantum efficiency, and spectral characteristics. In this work, we focused on growth parameter optimization for long-wave type-II strained layer superlattice (T2SL) PD structures grown on (211)B and (311)A GaSb substrates. Material and PD diode characteristics were compared with reference data obtained on (100)-oriented substrates. Material quality was evaluated by HRXRD, AFM, Nomarski microscopy, 77 K PL, and PD J-V and spectral testing. Photoluminescence and cutoff wavelength measurements for diode structures fabricated on (211)B and (311)A substrates demonstrate a significant redshift due to a reduction of the optical bandgap in the SL. The extent of redshift increases with superlattice period and Sb mole fraction in the InAsSb layers in the absorber. All wafers demonstrated reasonable surface morphology without surface corrugation, with minor variability in roughness. Redshift in 77 K PL and cutoff wavelength, in combination with high QE and low Jd, obtained from growths on these high-index substrates offer a potential path to achieve enhanced PD characteristics with reduced SL period for a given wavelength by comparison to (100) substrates.

In this work, we report the demonstration of quaternary GaInAsSb-based mid-wavelength infrared photodetectors with cutoff wavelengths longer than 4 μm at 300 K. Both interband cascade infrared photodetector (ICIP) with a three-stage discrete absorber architecture and conventional one-stage detector structures have been grown by molecular beam epitaxy and investigated in experiments for their electrical and optical properties. High absorption coefficient and gain were observed in both detector structures. The three-stage ICIPs had superior carrier transport over the one-stage detectors. A detectivity as high as 1.0 × 109 cm Hz1/2 W−1 was achieved at 3.3 μm for both one- and three-stage detectors under zero bias at 300 K. The implications of these results are discussed along with potential of GaInAsSb-based ICIPs for high-speed applications.

ABSTRACTIn this work, we investigate the thermal boundary resistance and thermal conductivity of GaN layers grown on Si with 100 nm AlN transition layers using time domain thermoreflectance (TDTR). The GaN layers ranged from 0.31 to 1.27 μm. Due to the challenges in determining the thermal boundary resistance of the buried interfaces found in this architecture, a new data reduction scheme for TDTR that utilizes a Monte Carlo fitting method is introduced and found to dramatically reduce the uncertainty in certain model parameters. The results show that the GaN thermal conductivity does not change significantly with layer thickness, whereas the resistance of the AlN layer decreases slightly with GaN thickness.

Thorough structural analysis is critical to understanding the effects of device design and modeling on type II superlattice (T2SL) based devices. In this work, structural parameters of T2SL infrared devices were uniquely determined by combining local structural parameters obtained by cross-sectional scanning tunneling microscopy (XSTM) with high resolution x-ray diffraction (HRXRD) spectra. The XSTM results were used to initialize and set tolerances for full dynamical simulation and simultaneous fitting of multiple HRXRD spectra. Using this method, we obtain unique, quantitative description of the superlattice structure, composition, and strain which can be used to evaluate the material effects on device performance.

The structural properties and band offset determination of p-channel staggered gap In0.7Ga0.3As/GaAs0.35Sb0.65 heterostructure tunnel field-effect transistor (TFET) grown by molecular beam epitaxy (MBE) were investigated. High resolution x-ray diffraction revealed that the active layers are strained with respect to “virtual substrate.” Dynamic secondary ion mass spectrometry confirmed an abrupt junction profile at the In0.7Ga0.3As/GaAs0.35Sb0.65 heterointerface and minimal level of intermixing between As and Sb atoms. The valence band offset of 0.37 ± 0.05 eV was extracted from x-ray photoelectron spectroscopy. A staggered band lineup was confirmed at the heterointerface with an effective tunneling barrier height of 0.13 eV. Thus, MBE-grown staggered gap In0.7Ga0.3As/GaAs0.35Sb0.65 TFET structures are a promising p-channel option to provide critical guidance for the future design of mixed As/Sb type-II based complementary logic and low power devices.

The structural, morphological, defect properties, and OFF state leakage current mechanism of mixed As-Sb type-II staggered gap GaAs-like and InAs-like interface heterostructure tunnel field effect transistors (TFETs) grown on InP substrates using linearly graded InxAl1-xAs buffer by molecular beam epitaxy are investigated and compared. Symmetric relaxation of &amp;gt;90% and &amp;gt;75% in the two orthogonal 〈110〉 directions with minimal lattice tilt was observed for the terminal GaAs0.35Sb0.65 and In0.7Ga0.3As active layers of GaAs-like and InAs-like interface TFET structures, respectively, indicating that nearly equal numbers of α and β dislocations were formed during the relaxation process. Atomic force microscopy reveals extremely ordered crosshatch morphology and low root mean square roughness of ∼3.17 nm for the InAs-like interface TFET structure compared to the GaAs-like interface TFET structure of ∼4.46 nm at the same degree of lattice mismatch with respect to the InP substrates. The GaAs-like interface exhibited higher dislocation density, as observed by cross-sectional transmission electron microscopy, resulting in the elongation of reciprocal lattice point of In0.7Ga0.3As channel and drain layers in the reciprocal space maps, while the InAs-like interface creates a defect-free interface for the pseudomorphic growth of the In0.7Ga0.3As channel and drain layers with minimal elongation along the Δω direction. The impact of the structural differences between the two interface types on metamorphic TFET devices was demonstrated by comparing p+-i-n+ leakage current of identical TFET devices that were fabricated using GaAs-like and InAs-like interface TFET structures. Higher OFF state leakage current dominated by band-to-band tunneling process due to higher degree of defects and dislocations was observed in GaAs-like interface compared to InAs-like interface where type-II staggered band alignment was well maintained. Significantly lower OFF state leakage current dominated by the field enhanced Shockley-Read-Hall generation-recombination process at different temperatures was observed in InAs-like TFET structure. The fixed positive charge at the source/channel heterointerface influences the band lineup substantially with charge density greater than 1 × 1012/cm2 and the band alignment is converted from staggered gap to broken gap at ∼6 × 1012/cm2. Clearly, InAs-like interface TFET structure exhibited 4× lower OFF state leakage current, which is attributed primarily to the impact of the layer roughness, defect properties on the carrier recombination rate, suggesting great promise for metamorphic TFET devices for high-performance, and ultra-low power applications.

In this work, 3-D Tri-gate and ultra-thin body planar InGaAs quantum well field effect transistors (QWFETs) with high-K gate dielectric and scaled gate-to-source/gate-to-drain (L SIDE ) have been fabricated and compared. For the first time, 3-D Tri-gate InGaAs devices demonstrate electrostatics improvement over the ultra-thin (QW thickness, T QW =10nm) body planar InGaAs device due to (i) narrow fin width (W FIN ) of 30nm and (ii) high quality high-K gate dielectric interface on the InGaAs fin. Additionally, the 3-D Tri-gate InGaAs devices in this work achieve the best electrostatics, as evidenced by the steepest SS and the smallest DIBL, ever reported for any high-K III–V field effect transistor. The results in this work show that the 3-D Tri-gate device architecture is an effective way to improve the scalability of III–V FETs for future low power logic applications.