Infineon Technologies (Austria)

This paper analyzes anti-phase parametric excitation for a resonant MEMS mirror by independently driving two out-of-plane electrostatic comb-drive actuators positioned at the left and right sides of the MEMS mirror, enabling a fast and reliable start-up from zero amplitude. Both the angular derivative of the comb drives' capacitance and the square wave driving signals are approximated by complex Fourier series, leading to a nonlinear model that describes the slow evolution of the amplitude and the phase of the MEMS mirror. The proposed model is validated through measurements, demonstrating strong agreement with the analytical results. A detailed discussion on injected and dissipated energy provides an intuitive understanding of the response curve for in-phase and anti-phase excitation signals with various duty cycles. Additionally, the initial start-up behavior of conventional in-phase parametrically excited MEMS mirrors is analyzed and compared to that of MEMS mirrors operated with anti-phase excitation, revealing an improvement of the start-up time by a factor between 8 to 50, depending on the operating point and condition.

Multi-bit quantization allows Delta-Sigma modulators to achieve low oversampling ratios (OSRs), improved jitter tolerance, and relaxed dynamic requirements of the loop filter, but face nonlinearity challenges in the feedback digital-to-analog converter (DAC), requiring complex calibration techniques. Dual quantization using digital DSM (DDSM) has been proposed to overcome this limitation, but state-of-the art DDSM suffers from limited resolution, stability concerns, and digital-analog matching requirements. This work applies a sturdy multistage noise shaping (SMASH) DDSM feedback DAC within a wideband DSM to address these issues. This results in low element mismatch sensitivity, eliminating the need for any DAC calibration. To reduce the effect of dynamic errors in the outer DAC, an inter-symbol-interference (ISI) shuffler is proposed and gain boosting is applied within the DAC elements to address memory effects due to parasitic capacitance. The DSM allows an excess loop-delay (ELD) <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$= 1.5\times T_{s}$</tex-math> </inline-formula> in the outermost feedback path to give enough processing time for the SMASH DDSM. The prototype implementation of the 3rd-order continuous-time (CT) DSM shows a 106.2dB spurious-free dynamic range (SFDR) in an 80MHz bandwidth without any DAC calibration. Using reference folding and shuffling in the internal Flash quantizer, the DSM is clocked at 2.75 GHz. Implemented in 28 nm CMOS, CT DSM achieves a competitive figure-of-merit (FOM) = 163.7dB for such extreme linearity.

This manuscript presents two approaches to improve the temperature effects on ring oscillators used in open-loop VCO-ADCs. The first approach is a circuit design optimization, which is based on an analysis of the ring oscillator against temperature, considering both gain and frequency deviations. It is shown that ring oscillators can be biased in regions with stable frequency or gain. The second technique is an oscillator stabilization circuitry for differential VCO-ADCs. We propose a common-mode feedback circuit that tracks the VCO frequencies to tune the common bias point. Therefore, intrinsic VCO variations are also compensated by this feedback. A proof of concept chip demonstrating both techniques has been implemented in 0.13μm. The chip measurements show a frequency and gain drift of 6% and ±0.25dB respectively between -40°C to 100°C. These measurements are comparable to the results achieved by digital temperature calibration without requiring an on-chip temperature sensor.

In this article, the hybrid dc-dc dual-path step-down topology is analyzed and selected for an automotive application due to its numerous benefits: it enables reduced inductor usage, which can be miniaturized, employs an auto-balanced flying capacitor, imposes limited stress on power switches, and offers, at the same time, a relatively wide conversion range. These features are achieved while maintaining the circuit complexity contained compared to many other competing hybrid topologies. A power loss analysis of the converter is carried out, which is exploited to obtain optimal sizing of the power stage and the inductor, and the chip architecture is described. Finally, the benefits of the topology are demonstrated experimentally through a highly-integrated prototype fabricated in 130nm CMOS technology, capable of converting an input voltage from the range 3.3-4.3V down to an output voltage in the range 0.7-1.2V, at a maximum power of 1.8W. The prototype, operating at a switching frequency of 2.5MHz, achieves a peak efficiency of 89.7% at a load current of 500mA, in a compact solution that features a power density of 1.73W/mm2.

This paper presents a high gain programmable 1.2V to 18V, 25-stage Charge Pump (CP) system with an on-chip generated clock signal for MEMS sensors biasing applications. This CP features an innovative structure to bootstrap the pumping switches that allows the use of specific high-voltage transistors to be avoided, since the voltage drop across any device is never higher than the supply voltage. The output voltage of the CP can be trimmed by varying its input voltage, provided through an Operational Transconductance Amplifier (OTA) feedbacked with a digitally programmable resistive divider, designed in such a way to get the regulated voltage to be an exponential function of the 6-bit trimming code. The clock signal to drive the CP is generated on-chip by a low-voltage and low-power Relaxation Oscillator (RxO). The proposed Charge Pump system reaches a maximum output voltage of 18V, draining from the 1.2V supply a total power of 2.6µW and using a total silicon area of 0.06mm<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup>.

Abstract Transmission electron microscopy (TEM) and related characterization techniques are widely used to inspect semiconductor devices. Conventional TEM (CTEM) and scanning TEM (STEM) methods mostly keep the incident electron beam at a fixed angle, aligned with the optical axis of the electron microscope. While effective in many scenarios, this invariance could limit the potential for more complex applications. We investigate a technique that allows us to acquire multidimensional data from a series of beam tilt angles. The acquired data can be further processed to provide more information and to reduce the possible errors associated with single data sets. In this paper, we demonstrate the advantages of this technique through several semiconductor use cases. These benefits include reducing unwanted background information in electric field mapping on a SiC film, enhancing strain mapping quality on a Si-SiGe multilayer structure and improving grain mapping on a 3D-NAND device. This beam-tilt technique can be executed via an automated script once the experimental conditions are optimized, paving the way for large-volume investigation through automated TEM.

Abstract This paper presents a large-signal analysis of radiofrequency power amplifier (PA) efficiency under the constraint of conjugate output matching. The study shows that in intrinsically low-efficiency operating regimes such as class-A, enforcing conjugate output matching leads to a factor-of-two reduction in efficiency with respect to an equivalent unmatched design, in agreement with the literature. However, when the amplifier is operated in class-AB and beyond, the efficiency penalty is reduced. Consequently, by appropriately adjusting the drive level and the PA bias point, it is possible to realize an output-matched PA with efficiencies comparable to those of unmatched designs. In addition to the analytical treatment, a practical topology and a design methodology for achieving the required output matching are presented. The findings are validated through transistor-level simulations of both bipolar and MOS RF amplifier designs.

The reliability assessment and failure analysis of Microelectromechanical System (MEMS) mirrors is a rather new research area, where especially the influence of environmental and mechanical loads on the performance needs to be evaluated. The aim of this work is to test the reliability of two-dimensional (2D) resonant MEMS mirrors, which are driven electrostatically, under applied stress in order to find out after which time and at which stress levels the function of the mirror is affected or a breakage occurs. With the help of the used test setup several mirrors could be tested simultaneously and different mirror parameters could be logged. Measurements have been executed with a duration of approximately one month, where the mirrors were stressed by increasing the oscillation angle over time. The results showed that there are mirror parameters, which may indicate a failure of the mirror before it occurs. Especially a negative drift of the mirror frequency was observed before breakage. Additionally the results showed a correlation between temperature and mirror frequency and information about the distribution of the stress levels at which the mirrors break was gathered.

Multi-bit (MB) quantization allows Delta-Sigma Modulators (DSMs) to achieve low oversampling ratios (OSRs), improved jitter tolerance, and relaxed dynamic requirements of the loop-filter (LF) while maintaining high maximum stable amplitude (MSA). However, the nonlinearity caused by the outermost feedback digital-to-analog converters (DACs) is challenging. This work applies a Multi-stage noise SHaping (MASH) digital DSM (DDSM) in a dual quantization (DQ) continuous-time deltasigma modulator (CT-DSM), resulting in significantly relaxed element mismatch sensitivity while eliminating the need for DAC calibration. In addition, high jitter robustness is achieved by combining MB quantization with a 4-tap finite impulse-response (FIR) filtering. Dual return-to-zero (DRZ) is introduced into the 4-tap FIR to reduce the effect of dynamic errors. Finally, the power-efficient tri-level DAC encoding is combined with a midtread asynchronous successive-approximation-register (A-SAR) to improve matching and noise. The prototype of the CT-DSM shows a 102.3 dB spurious-free dynamic range (SFDR) in a 3 MHz bandwidth. Implemented in 28 nm CMOS, the CT-DSM is clocked at 120 MHz and achieves a Schreier figure of merit of 170 dB.