Infineon Technologies (Germany)

ABSTRACT Boron nitride (BN) is considered for several applications in microelectronics, such as thermal management, optoelectronics, or as memristors. BN can be deposited with different deposition methods, but any integration in the back‐end‐of‐the‐line limits the deposition temperature to approximately 400°C. Further requirements include high crystal quality, sufficient film stability, and a high deposition rate to limit process costs. In particular, investigations into thin film stability and high deposition rates have rarely been conducted. Here, we propose reactive pulsed direct current sputtering at 250°C from a pure boron target and demonstrate the deposition process for stable nanocrystalline turbostratic BN. A substrate bias voltage between the plasma and sample reduces excess boron in the film and enhances its crystallinity. The process effectively prevents the formation of boric acid and ammonium borate hydrate. The stable BN films have a crystallite size of approximately 5 nm and an out‐of‐plane texture. Leakage current investigations demonstrate the insulating properties of the films. A high deposition rate of 81.6 nm min – 1 and the use of state‐of‐the‐art sputter hardware allow the immediate integration of sputtered BN into semiconductor device process lines.

This paper analyzes anti-phase parametric excitation for a resonant MEMS mirror by independently driving two out-of-plane electrostatic comb-drive actuators positioned at the left and right sides of the MEMS mirror, enabling a fast and reliable start-up from zero amplitude. Both the angular derivative of the comb drives' capacitance and the square wave driving signals are approximated by complex Fourier series, leading to a nonlinear model that describes the slow evolution of the amplitude and the phase of the MEMS mirror. The proposed model is validated through measurements, demonstrating strong agreement with the analytical results. A detailed discussion on injected and dissipated energy provides an intuitive understanding of the response curve for in-phase and anti-phase excitation signals with various duty cycles. Additionally, the initial start-up behavior of conventional in-phase parametrically excited MEMS mirrors is analyzed and compared to that of MEMS mirrors operated with anti-phase excitation, revealing an improvement of the start-up time by a factor between 8 to 50, depending on the operating point and condition.

This work presents a complete deep-learning-driven automation flow for designing ultra-low-power subthreshold operational transconductance amplifiers used in electronically tunable gm-C resonator and anti-resonator circuits for speech vowel processing. A multi-task learning neural network is trained as an accurate and extremely fast metamodel (surrogate) of an 8-parameter operational transconductance amplifier topology in 350 nm CMOS process node. Using only 60000 Latin-hypercube-sampled circuit simulations for training, the metamodel predicts DC power consumption, total transistor area, and DC transconductance with average errors of 2.9%, 5.0%, and 7.3%, respectively. The trained model is then coupled with the NSGA-II multi-objective genetic algorithm to instantly generate Pareto-optimal trade-offs between power and area for any designer-specified gm value in the 45-55 nA/V range typical of vowel formant filters. Compared to conventional simulation-in-the-loop NSGA-II optimization, the proposed flow reduces the total design time from 25 h to 7 h, a 3.5 times speedup, and against the standard human design methodology, the acceleration is higher than 20 times. The methodology enables on-the-fly power/area optimization of all operational transconductance amplifiers in sixth-order tunable vowel filters without need for re-design.

ABSTRACT This article features a comprehensive methodology for analyzing and optimizing PWM dead time in automotive traction inverters, applicable to a wide range of power devices, including Si IGBT/Diodes, SiC MOSFETs, and Si/SiC Fusion switches. The proposed methodology enables a systematic comparison of dead time characteristics, focusing on part‐to‐part tolerances and operating point‐dependent influence factors. Three traction inverter systems, each in the 200–300 kW class at 470 V, were built up utilizing Si IGBT/Diode, SiC MOSFET, and Si/SiC Fusion switches from the latest automotive‐released technology. The impact of PWM dead times on power losses was experimentally investigated for all three inverter systems, supporting the analytical model. Key findings from the experimental data include: (1) PWM dead times can account for more than 10% of the total inverter power losses in high current density SiC MOSFET inverter designs operating at typical automotive switching frequencies of 10 kHz; (2) Optimizing PWM dead times in Si/SiC Fusion power modules leads to up to a 5% reduction in total inverter power losses and improved current sharing, resulting in lower thermal stress—This was evaluated using thermal infrared measurements from the Si/SiC Fusion inverter prototype; 3) Optimized PWM dead times can reduce total harmonic distortion at light load conditions by up to 2%–3% for IGBT/Diode and up to 4%–5% for SiC MOSFET and Si/SiC Fusion inverter systems; (4) A sensitivity study in addition revealed that Si/SiC Fusion switches exhibit the most stable dead time settings under parameter variations. The benefit of optimized versus conventional 2 PWM dead times would result in an annual energy saving of approximately 6 GWh per 1 million vehicles. This highlights the significance of optimized PWM dead times in automotive traction inverters operating at typical switching frequencies of 10 kHz. The goal of this investigation is to support the development of reliable and efficient automotive traction inverters, with the methods presented being applicable to other applications as well.

This article proposes the novel use of the asymmetrical half-bridge flyback (AHBF) topology with a bidirectional behavior. AHBF has seen an increase in industrial use in recent years due to its advantages over other topologies, such as its high power density, low component count and wide voltage range by exploiting the resonance between the transformer leakage inductance and an added resonant tank. Up to now, the AHFB topology has been used as a step-down converter; furthermore, by making use of its synchronous rectifier, a resonant flyback-forward topology with step-up function is obtained. The proposed isolated bidirectional converter can achieve high voltage conversion rate with elevated efficiency and power density. To test the theoretical analysis, a 240 W prototype with 320 to 400 V on the high voltage side and 12 to 24 V on the low voltage side built with GaN technology is carried out in the laboratory. A high boost and buck capability with wide voltage range is obtained, as well as reaching a maximum efficiency in step-down mode of 97.97% and of 97.76% in step-up configuration. This makes AHFB an attractive alternative for bidirectional conversion applications.

Active Thermal Control (ATC) strategies are increasingly used to improve the reliability and thermal performance of power electronic converters. Among these strategies, gate voltage modulation offers a way to influence the power losses without compromising signal quality. However, existing implementations often require multiple isolated supplies or modifications in high-voltage side circuitry, increasing complexity and cost. This work presents a Variable Voltage Supply (VVS) that enables gate voltage modulation without requiring signal isolation or changes to the gate driver high-voltage side. The circuit is based on a fixed-output flyback supply design, modified to allow multi-level programmability using primary-side regulation and a digitally controlled resistor network. This configuration enables microcontroller-based selection of four output levels (15 V, 17 V, 18 V, 20 V), with a voltage slew rate of 60 mV/<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$\mathrm{\mu }$</tex-math></inline-formula>s. The added functionality results in a component cost of 12.41 €, representing an increase of 0.15 € compared to the original design. The circuit is compatible with both MOSFET and IGBT technologies, and can be directly integrated into existing converter platforms. The concept has been validated experimentally, and results confirm that increasing the gate voltage reduces steady-state junction temperature. In addition, the article also discusses the main limitations of the approach (e.g., increased short-circuit stress at high gate voltages) and outlines potential improvements including dual-polarity supply extension and closed-loop ATC strategies, among others.

Integrated cryogenic analog multiplexers are essential for scaling up trapped ion quantum computers (TIQC). They require high-voltage devices, such as LDMOS, to operate within the required voltage range of upto ±40 V. However, at cryogenic temperatures, below 40 K, LDMOS devices exhibit a diode-like behavior, leading to nonlinear on-resistance at low V<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DS</inf>. This negatively affects settling time and transfer function linearity of the required analog multiplexers. Previous work on cryogenic LDMOS focused on characterizing and modeling their behavior. This work explores the use of a field plate to improve the on-resistance performance of LDMOS devices at cryogenic temperatures. Our field plate engineered device was fabricated and measured at cryogenic temperatures alongside a baseline device. Our key findings include: 1) a field plate is essential at cryogenic temperatures; 2) it reduces on-resistance by six orders of magnitude at low V<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DS</inf>; 3) it degrades the breakdown voltage; 4) device nonlinear region span decreases to 40 mV compared to the previous threshold of 400 mV. Finally, TCAD-based cryogenic simulations demonstrate that the remaining threshold stems from an energy barrier in the conduction band at STI corners. These results show for the first time that regaining the linear behavior of LDMOS devices’ on-resistance at cryogenic temperatures can be achieved, which is essential to scale up the number of qubits and hence bring quantum computers to commercial use.

<strong class="journal-contentHeaderColor">Abstract.</strong> Since June 2019, a scanning airglow camera is operated operationally every night at DLR Oberpfaffenhofen (48.09&deg; N, 11.28&deg; E), Germany. It provides nearly all-sky images (diameter 500 km) of the OH* airglow layer (height ca. 85&ndash;87 km) with an average spatial resolution of ca. 150 m and a temporal resolution of ca. 2 min. We analyse about three years (941 nights between October 2020 and September 2023) of OH* airglow all-sky images for spatially confined wave structures with horizontal wavelengths of ca. 20 km and less. Such structures are often referred to as ripples and are considered to be instability structures. However, Li et al. (2017) showed that they could also be secondary waves. While ripples move with the background wind, secondary waves do not. To identify small-scale and spatially confined structures, we adapt and train YOLOv7 (You Only Look Once, version 7), a machine learning approach, to determine their position and extent on the sky as well as their horizontal wavelength. Those wavelengths are compared to two-dimensional FFT (Fast Fourier Transform) results. We analyse the seasonal variations in the propagation direction and horizontal wavelengths of these structures and deduce that instability signatures are observed especially in summer. Finally, we introduce a concept for &ldquo;operating-on-demand&rdquo; in order to derive energy dissipation rates from our measurements.

This paper presents a Model-Driven Architectureinspired generation methodology for auto-generating C and Rust firmware, enabling the development of complex embedded cross-language systems. The proposed approach leverages the combined power of existing software generators to generate firmware, ensuring interoperability with existing C-based systems while allowing for a gradual migration towards modern Rust-based systems. This enables an improved support of the safety features available in Rust, compared to an interfaced C-code called from Rust, which cannot provide these guarantees. The paper provides an overview of the fundamental building blocks of the approach and discusses the challenges and advantages of chaining both generators. Our Halstead measurments highlight the advantages of utilizing this Model-Driven approach in reduction of manual effort and the risk. This reduction is comparable to the results found in state-of-the-art literature, as highlighted by the comparison presented in this paper, but provides dual-language embedded code. This paper forms another building block towards generating hardware-dependent complex software platforms.

In the semiconductor industry, a lot refers to a batch of singulated chips in the Backend process, where the chips in a lot undergo several test measurements. Based on the failure percentage of the chips, a lot stops for more analysis, which is called