Inphi (United States)

When RTL designers define the hierarchy of a system, they exploit their knowledge about the conceptual abstractions devised during the design and the functional interactions between the logical components. This valuable information is often lost during physical synthesis. This article proposes HiDaP, a novel multilevel algorithm that uses RTL information and analytical methods for the macro placement problem of modern designs dominated by multicycle connection pipelines. By taking advantage of the hierarchy tree, the netlist is divided into blocks containing macros and standard cells, and their dataflow affinity is inferred considering the register latency and flow width of their interaction. The layout is represented using slicing structures and generated with a top-down algorithm capable of handling blocks with both hard and soft components. An adaptive multiobjective cost function is used to simultaneously minimize wirelength, timing, overlap, and distance to preferred locations, which can be user defined or generated by analytic methods (spectral and force directed). These techniques have been applied to a set of large industrial circuits and compared against state-of-the-art commercial and academic placers, and also to handcrafted floorplans generated by expert backend engineers. The proposed approach outperforms previous algorithmic methods and can produce solutions with better wirelength and timing than the best handcrafted floorplans. Post-routing layouts are almost brought to timing closure and DRC cleanness with minimal engineer modification, showing that the generated floorplans provide an excellent starting point for the physical design flow and contribute to reduce turn-around time significantly.

Ring oscillator (RO)-based frequency synthesizers enable cost-efficient and scaling-friendly implementation, but also result in worse phase noise compared to LC-based alternatives. There has been increasing interest in injecting a low-noise reference clock signal to the RO to refresh the accumulated jitter, as seen in multiplying delay-locked loops (MDLLs) and injection-locked phase-locked loops (1L-pLLs). The main challenge of this architecture is that the injection signal derived from the reference clock is not perfectly aligned with the RO phase at the injection node, hence spurious tones are generated, and this phase alignment issue is especially exacerbated in fractional-N 0peration as the injection time paint must gradually drift away from the reference clock phase [1]. One way of achieving this required phase drift is by tuning digital-to-time converters (DTCs) according to a fractional frequency multiplication ratio; however, DTC offset and gain errors can introduce spurs. Several works have demonstrated DTC calibration, but are either limited to foreground calibration or incur an additional time-to-digital converter (TDC) [2], [3]. To further suppress injection-locking-induced spurs, we propose a background DTC calibration scheme that: 1) simultaneously estimates DTC gain and offset errors by occasional injection squelching; 2) performs two-point gain and offset error correction in the respective analog and digital domains; 3) uses TDC dithering [4] to enhance error estimation accuracy; and 4) removes dithering noise with an adaptive comb-filter-assisted cancellation loop. To prove the concept, a fractional-N digital MDLL using the DTC calibration scheme is implemented in 65nm CMOS and demonstrates 1.67ps RMS jitter and -60dBc fractional spur with 26dB spur suppression.

Driven by the proliferation of rich media services and a drastic increase of data availability, the demand for high-speed data transfer in the data center continues to grow at greater than 26 percent year-over-year [1]. This urges the imminent solution of top-of-rack switches in hyperscale networks with faster I/O interfaces to simultaneously support both low power and high throughput. Supporting the substantial bandwidth increase has driven the development of new electrical and optical interconnect standards which enable 100Gb/s per channel including IEEE 802.3ck and CEI-112G with PAM-4 modulation in conjunction with forward error correction (FEC) [2]. For long-reach applications, a transceiver architecture with >40dB channel equalization is critical due to the extra 8-10dB package insertion loss. To resolve those bottlenecks, this work presents an ADC-DSP based PAM-4 transceiver capable of equalizing >41.5dB lossy channels and achieving 112Gb/s per channel and 896Gb/s overall retimer throughput in 7nm FinFET.

PAM-4 has become the mainstream modulation format for short-reach ($\lt2$ km) optical interconnects at data rates of 50Gb/s and above [1, 2]. For more efficient utilization of optical bandwidth in large-scale data centers, data rates of 100Gb/s per wavelength are required. This data rate imposes aggressive requirements on transceiver bandwidth (BW) and jitter. In addition, due to thermal constraints, transceivers must consume low power to help meet optical module power budgets specified by the multisource agreements (MSA) such as QSFP-DD and OSFP. This paper presents a low-power and low-jitter 4 × 100Gb/s transceiver for PAM-4 optical interconnects.

The authors compare transmission reach of 100 Gb/s four‐level pulse amplitude modulated signals over single‐span systems constructed with three optical fibre types. They demonstrate reach up to 160 km with fibres having ultra‐low attenuation, one with a large effective area.

The field of machine learning potentially brings a new set of powerful tools to optical communications and photonics. However, to separate hype from reality it is vital that such tools are evaluated properly and used judiciously.

A key challenge in optical networking is the development of low-power transceivers that interface to optical sub-assemblies (TOSAs & ROSAs). While SiGe technologies are often selected for jitter performance with optical links, especially on the egress path to the transmit optics, lower-power and higher levels of digital integration often result from CMOS approaches . This paper describes a generic CMOS 25-to-30Gb/s SerDes for use within CDR or gearbox applications, targeting the draft requirements of the OIF 28G-VSR standard and suitable for both 100GBASE-LR4/OTL4.4 gearbox and retiming applications, including CFP and CFP2.