Instituto de Microelectrónica de Sevilla

We present a neuromorphic circuit cell that integrates a volatile VO<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> neuron with a non-volatile HfO<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> memristive synapse, enabling autonomous local plasticity in a compact, CMOS-compatible building block. Unlike conventional neuromorphic implementations where neurons and synapses are separated and coordinated by peripheral circuitry, the HfO<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> memristor is embedded directly in the leak path of a VO<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> integrate-and-fire neuron. As a result, the neuron’s spike dynamics directly modulate the synaptic conductance, which in turn reshapes neuronal excitability. Using experimentally calibrated Verilog-A models and electrical simulations, we demonstrate stable firing-rate adaptation, long-term conductance evolution driven by neuronal activity, and compatibility with standard 1T1R programming schemes. This unified neuron–synapse cell forms a device–circuit primitive where volatile and non-volatile dynamics are co-designed at the cell level, enabling scalable local plasticity without peripheral control circuitry.

In this article, we present a lightweight peripheral of the Advanced Encryption Standard (AES) algorithm suitable for its implementation as a memory mapped peripheral in RISC-V cores. The peripheral is based on an 8-bit serial implementation of AES, which achieves a drastic reduction in the time required to encrypt a message with a reduced increase in resource consumption. The peripheral is compared in terms of resource utilization and timing with a software implementation of AES, tinyAES-c, and a hardware implementation that employs a more common 128-bit datapath using the Series-7 FPGA technology of the manufacturer AMD-Xilinx. The results show that the system using the peripheral achieves a speed 71.84 times faster than the software implementation, with a 46.37% increase over the logic used to implement the RISC-V processor.

Bias Temperature Instability (BTI) poses a significant challenge in ensuring the reliability of digital systems, affecting the delay of digital logic gates, which ultimately can lead into timing failures. Sophisticated defect-centric models have been developed and successfully calibrated against empirical data to forecast the impacts of BTI at the device level. However, their application to large-scale digital circuits operating under realistic workloads over typical system lifetimes is limited because of the computational complexity of defect-centric models. To make the application of aging models in that context feasible, a useful technique is to compress the transistor workloads into simplified and hence manageable representative workloads. While fast in terms of execution speed, previous techniques struggle with accuracy when predicting aging degradation, and can reach a very high average error in threshold voltage increase prediction. In this work, we review the compression techniques described in the literature and propose two novel approaches that surpass existing ones in terms of accuracy, which is demonstrated for a complex digital design used as benchmark. Specifically, our best compression technique matches the predictions obtained through the reference uncompressed workloads, introducing negligible error, and maintains low execution times to efficiently and accurately scale defect-centric models to the circuit level.

This paper presents an innovative T/Y-mazebased wireless power transmission (WPT) system designed to monitor spatial reference memory and learning behavior in freely moving rats. The system enables uninterrupted stimulation and neural recording experiments. An array of resonators covers the entire maze, ensuring scalability across various configurations. The array is designed to provide a natural localization mechanism, directing the Tx power toward the location of the $\mathbf{R x}$ coil. The wireless power delivery throughout the maze was studied by comparing different $\mathbf{T x}$ array configurations, including floating, series, and parallel resonators. The calculated Specific Absorption Rate (SAR) in the rat tissue model is $1.7 \mathrm{~W} / \mathrm{kg}$ at a power carrier frequency of 13.56 MHz. The 128 cm maze array achieves $94 \%$ homogeneity and ensures power transfer efficiency of over $30 \%$, while continuously delivering more than 60 mW in the series configuration.

Optical ultrasound sensors can achieve high sensitivity, small element size, and broadband frequency response. Polymer plano-concave microresonators (PCMRs) are among the most sensitive ultrasound sensors, but achieving further increases in sensitivity is limited by the optical absorption of the polymer cavity material. To address this, the use of fused silica as the cavity material is investigated. We present findings supporting the assertion that the low compressibility of fused silica compared to polymeric materials can be overcome by exploiting its extremely low optical absorption to achieve high Q-factors approaching 106. We also show that the high Q-factors can introduce laser phase noise unless very narrow linewidth (<150 Hz) laser sources are employed. In this work, a fused silica PCMR ultrasound sensor is reported that has an NEP of 0.7 mPa/√Hz, a broadband frequency response with a -3 dB bandwidth of 2.5 MHz, and low directional sensitivity.

Abstract The realization of artificial neural circuits requires synaptic materials and devices that show adaptation at different time scales to modulate signal transmission between neurons according to the desired applications. Sensory‐motor and intelligence operation in the brain relies on the dynamical properties of synapses that adapt to the frequency and synchronization of voltage spikes. The properties of potentiation and depression of the synapse conductivity control the plasticity and adaptation of synapses. Here, the general dynamical properties of ionic or electronic current conduction that form the main rules of synaptic activity are discussed. The basic model requirements of a memristor or chemical inductor to produce an adaptation of conductance to incoming stimuli are established. The synaptic response can be described by the combination of three factors: A conduction process that depends on an internal state variable x; this variable causes rectification at an onset voltage; it also causes a memory, characterized by a delay in response to the stimulus. Diverse diagnosis methods are described that connect the nonlinear time response, the nonlinear cycling of current–voltage curves, and the linear frequency response of impedance spectroscopy, to assess the adaptation properties.

This demo shows a toolbox for the optimization and automated high-level design of Analog-to-Digital Converters (ADCs). The tool integrates Artificial Neural Networks (ANNs) with behavioral simulation to optimize the high-level sizing process, mapping system-level specifications to building-block requirements. ANNs are trained to determine the optimal ADC architecture based on given specifications, as well as the ideal set of design parameters that meet these requirements. The ANN-generated designs are refined through iterative simulations to achieve the best figure of merit. The toolbox, applied to Sigma-Delta Modulators (Σ∆Ms), features a Graphical User Interface (GUI) implemented in MATLAB, which guides users through the entire process—from specifications to verification <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1</sup>

This demo shows how to use the You Only Look Once (YOLO) version 8 framework to identify radio-frequency (RF) signals for spectrum sensing in Software-Defined-Radio (SDR) and Cognitive-Radio (CR) systems. To this purpose, a trained YOLOv8 nano framework was embedded in an IoT device based on a Raspberry Pi 5 and connected to an ADALM-PLUTO SDR board to detect and classify the activity of RF frames around the industrial, scientific, and medical (ISM) frequency band. This framework detects wireless standards such as Bluetooth and WiFi. This hardware demonstrator operates in real-time and can detect RF frames showing its potential application in SDR/CR terminals<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1</sup>.