Isothermal Community College

Traumatic hemipelvectomy (THP) is a catastrophic injury associated with high-energy trauma and high mortality. THP has been defined as a complete dislocation of the hemipelvis, often with disruption through the symphysis pubis and sacroiliac joint with concurrent traumatic rupture of the iliac vessels. Despite recent advances in prehospital resuscitative techniques, the true incidence of THP is difficult to ascertain because many patients die before hospital arrival. The leading causes of death associated with THP include blood loss, infection, and multiple system organ failure. Recognition and immediate intervention for these injuries is imperative for survival. The initial assessment includes a thorough physical examination assessing for signs of arterial damage and other associated injuries. Hemorrhage control and vigorous resuscitation should be prioritized to combat impending exsanguination. Emergent amputation has been found to be a lifesaving operation in these patients. The basis of this approach is rooted in achieving complete hemostasis while reducing complication rates. Understanding the nature of these massive pelvic injuries, the role of early amputation, and the importance of subspecialty communication can improve survivability and optimize patient outcomes.

The demand for increased computational power is continuing at an unrelenting pace. To meet this demand, board vendors are forced to increase the density of their systems. For example, some vendors today offer 1U servers with four processor motherboards. Accompanying this demand for increased computational power is an increasing demand for memory. With the introduction of multi-core microprocessors, the demand for memory will increase further. Traditional air-cooled memory modules, i.e., DIMMs, are increasingly consuming greater levels of motherboard real estate. In addition, rising internal system ambient temperatures are leading to increased failures of the memory, hard drives, power FETs, and other motherboard devices. This combination of events has created an opportunity for dense stacked memory that can either be air-cooled in nominal densities, or liquid-cooled in more extreme densities. The authors have designed, built, and are in the process of testing a dense dual Opteron board. The board conforms to the CompactPCI standard (6U × 160 mm), and houses four mezannine cards that can host up to 4 GB of dense stacked memory apiece (total of 16 GB for the board). The stacked memory is built using 512 Mb die, and is deployed in stacks of 8 and 10. The board is housed in a global SprayCool™ chassis that utilizes a dielectric fluid to cool all components on the board. As part of the development of the board, the design entailed CFD simulations of the full board, including the memory mezannine cards. The CFD simulations show that the memory junction temperature of 100°C can be maintained via spraying the backside of the mezannine cards, and by delivering enough spray to achieve a heat transfer coefficient of 0.05 W/cm2-K. Heat transfer coefficients an order of magnitude higher than 0.05 W/cm2-K are readily achievable with spray evaporative cooling, leaving headroom for significantly denser memory packages. Results from the comparison of the CFD simulations of the mezzanine cards to experimental temperature measurements will be presented for a variety of environmental conditions. The benefits of stacked memory will also be discussed from the standpoint of reliability, board density, system density, and benchmark performance.