LSI Solutions (United States)

The MitraCut procedure employs beating heart transapical (TA) cannulation and endoscopic scissors for dividing the anterior mitral leaflet (AML) to prevent left ventricular outflow tract (LVOT) obstruction in transapical transcatheter mitral valve replacement (TA-TMVR). We present the first multicentre experience of the MitraCut procedure prior to TA-TMVR to prevent LVOT obstruction. In 6 European centres, the clinical outcomes of all 13 high-risk patients who had undergone the MitraCut procedure during TA-TMVR procedures were retrospectively reviewed regarding technical success, procedural details and outcome. The MitraCut procedure was successfully completed in 11 patients with 1 cutting attempt, while 2 patients had 2 cutting attempts, with an average procedure duration of 9.0±5.4 min. No patient demonstrated postoperative LVOT obstruction, and all mitral valve (MV) prostheses were competent throughout the follow-up period. However, 1 patient developed a MitraCut-related paravalvular leak (PVL; technical success rate: 12/13). The mean LVOT gradient was 3.9±4.4 mmHg directly after valve expansion and 3.6±3.1 mmHg at follow-up. In-hospital and 30-day mortality were 0%. One patient experiencing MitraCut-related PVL was successfully treated by interventional PVL closure (reintervention rate: n=1). One patient died at 47 days due to cardiac arrhythmia, unrelated to the AML-directed procedure. The mean follow-up at the time of data analysis was 52±34 days. The MitraCut procedure was effective and reproducible for preventing potential LVOT obstruction in TA-TMVR patients during its initial exploration in 6 European hospitals. Considerations regarding the scissors' characteristics, their handling and cut length are mandatory for safe performance of the procedure.

A fully functional PowerPC476FP SoC communication processor with 4MB eDRAM System Cache achieving 2GHz/Core, in a 4 × 2.5DMIPS/Core/MHz configuration is qualified using physics-of-aging models in a 45nm SOI CMOS technology node including a logic and deep-trench (DT) eDRAM optimized semiconductor process. A novel circuit-depend F<;sub>MAX<;/sub>, Power, and Process optimization methodology that resolves technology reliability limitations (including Stress Migration, EM, BTI, HCI, TDDB, Defects, Package) without product burn-in, while delivering a 9.26% improvement per bin in energy-efficiency across 16 bins and up to 43.9% reduction in failure rate compare to equivalent circuits without the novel optimization methodology is described. Measured results show functional operation with a voltage range of 0.75V to 1.125V, a temperature range of -40C to 125C, speed of 1.8+ GHz at 0.96V, 110C and 90-100% yield performance, for a product lifetime specification of 88KPOH & 2750 ON/OFF cycles. These results demonstrate the highest reliability-aware functional performance reported to date with a 45nm nominal process at 0.9V for a 32-bit Quad-Core communication processor with asymmetric and scalable architecture while achieving the highest reported enterprise-level energy efficiency compare to Quad-Core communication processors in the same class. The technical contributions in this work enables a growing industry trend towards multi-radio ultra-compact stackable base stations designed to drastically reduce the entry price level per base station, enhance scalability and up-gradeability, significantly lower power consumption and enhance flexibility.

Non-binary low-density parity-check (NB-LDPC) codes are robust to various channel impairments. The excessive computational complexity and memory usage of the existing decoder designs are considerably expensive for practical applications. Based on a newly proposed simplified min-sum algorithm, which only has 0.05-0.1 dB performance loss against the sum-product algorithm, a highly efficient decoder architecture is developed. Compared with the existing works, our design has three advantages. First, the design increases the parallelism and throughput of the decoder by three to four times. The implementation results for the decoder show high throughput of 64 Mbps at 15 iterations. Second, this design saves memory usage by 38% to 76%. Third, this design shows 2.64 × area efficiency improvement even compared with the most state-of-the-art design.

This paper examines different designs for combined channel estimation and decoding for a point to point time varying frequency selective fading channel. The channel state information (CSI) is not known a priori at either the transmitter or the receiver. Channel estimation is performed through a combination of conventional pilots and manufactured pilots from previously decoded data. The paper examines how different interleaver structures affect the tradeoff between achievable rates, delay and complexity. When there is no delay constraint at all, the conventional pilots can be eliminated completely and a proper interleaving scheme can convert half the symbols into manufactured pilots. When there is a delay constraint, the paper explores various interleaver structures that combine the conventional pilots with the manufactured pilots in different ways to get much better achievable rates than conventional pilot-symbol aided channel estimation.

The usefulness of scan tests with multiple fault activation cycles to improve the coverage of transistor stuck-open faults is investigated. A recent work demonstrated that tests with more than one fault activation cycle can detect additional transition delay faults and inline resistance faults when compared to two-pattern tests applied using the broadside or skewed-load methods. We extend this work to show that such tests can also be used for testing additional transistor stuck-open faults. Experimental results for coverage improvement in several ISCAS-89 benchmark circuits will be discussed.

By disassociating from the conventional planar Nch FET structure, a new step split channel device with a new mechanism of ballistic channel hot electron (CHE) injection promises viability in future EEPROM/flash applications. The new non-planar device exhibits fast program of /spl sim/100 ns, at a maximum internal voltage of 5 V and at low currents of less than 10 /spl mu/A.

In a stack NOR flash cell, a small vertical (step) channel has been added to the conventional horizontal channel, to reduce the operating voltages for CHE injection and FN ejection. Devices and processes have been optimized based on extensive 2D simulations, with hardware results showing a 1-1.5 V reduction in the drain voltage requirement, and more than one order of magnitude increase in injection efficiency.