Macronix International (Taiwan)

Neural networks have demonstrated superior performance over rule-based and model-based approaches in processing noisy sensing data. However, their substantial computational and energy demands hinder deployment in battery-powered embedded systems. Computing-in-Memory (CIM) devices offer a promising alternative by significantly reducing energy consumption. Prior work [2] achieves this by leveraging a non-von Neumann architecture, which minimizes data movement between memory and compute units, thereby mitigating the memory wall bottleneck. Despite these advantages, analog CIM (ACIM) systems face several key challenges, including analog noise, limited numerical precision, and increased hardware complexity. While cloud-based neural networks are still dominant, emerging applications increasingly demand real-time, privacy-preserving inference on-device. For instance, facial authentication requires local execution on edge devices to ensure low-latency responsiveness and to protect user privacy. CIM architectures are particularly well-suited to these scenarios due to their tightly integrated memory-compute structure, offering low-latency and energy-efficient inference capabilities.

Vector similarity search (VSS) is crucial in many AI applications, such as few-shot learning (FSL) and approximate nearest-neighbor search (ANNS), but it demands significant memory capacity and incurs substantial energy costs for data transfers during large-scale comparisons. Various in-memory search technologies have been developed to improve energy efficiency, with NAND-based multi-bit content-addressable memory (MCAM) standing out as a promising solution for its high density and large capacity. MCAM can operate in exact-search (ES) mode, supporting only perfect matches with low energy cost, or in approximate-search (AS) mode, enabling flexible VSS. However, AS mode incurs significant energy waste when comparing queries with non-target stored vectors. To address this issue, we propose Hybrid-M, a 3D NAND-based in-memory VSS architecture that integrates both modes into a single hybrid matching process, using ES mode as a filter to reduce redundant searches for AS mode. We apply three techniques to optimize this integration: range encoding for multi-level cells (MLC) to enhance filtering, search voltage shifts to mitigate the impact on AS accuracy and reduce matching currents, and a filtering-aware training method to further improve reliability and energy efficiency. Results show that Hybrid-M achieves comparable accuracy while reducing energy consumption by 67% to 83% compared to MACM-based VSS using only AS mode, across various many-class FSL and ANNS workloads.

We developed a monolithic 3D (M3D) macro with CMOS and ambipolar SONOS tunnel FET (TFET) for edge-AI computing applications. The substrate-level (Tier-1) CMOS transistors for logic operations have good thermal stability to withstand the low-temperature TFETs fabrication process (< 400℃) above the Si-substrate (at Tier-2). The ambipolar SONOS-TFET, which is composed of intrinsic poly-Si channel with laser recrystallization process, provides large memory window (>6V) for multi-level data storage (> 10 levels). Among the potential applications is the in-memory range search for the memory augmented neural network (MANN). The data range can be pre-defined by different TFET device lengths and/or by varying the drain bias. The novel range computing macro enhances data matching capability between the query and objects using the K-nearest neighbor (KNN) algorithm. Simulation experiments with the CUB-200 dataset showed high voting accuracy up to 86.5% (Cosine similarity baseline: 87.7%) in few-shot learning (FSL) scenarios. The effects from TFET subthreshold swing, matching range, and input dimensions on the MANN accuracy optimization are discussed.

Wafer edge engineering is crucial in 3D memory process. Poor wafer edge integrity can lead to several issues. Film peeling in subsequent processes induced by severe wafer edge topography may become a defect source. Inadequate conductive film step coverage around the wafer edge can lead to etching or deposition arcing due to insufficient discharging pathways. Deeper etching requires longer etching time and higher etching power, both of which exacerbate the risk of arcing effects. To mitigate these challenges and maintain wafer edge integrity during 3D memory process, the application of various wafer edge treatments is essential. The methods include Negative Tone Development (NTD) with Wafer Edge Exposure (WEE) for wafer edge protection, film removal using dry or wet etching processes, selective wafer edge exposure, and edge coat. In this study, we optimized the edge coat process to achieve the desired coating width and thickness, ensuring its integration with 3D memory etching processes. Optical Microscope (OM) and Scanning Electron Microscope (SEM) were used to observe the condition of wafer edge and coating performance on wafer. Special efforts were made to minimize the hump height of the edge coat to meet the process requirements for tri-layer hard-mask applications in the etching process.

While memory-augmented neural networks (MANNs) offer an effective solution for few-shot learning (FSL) by integrating deep neural networks with external memory, the capacity requirements and energy overhead of data movement become enormous due to the large number of support vectors in many-class FSL scenarios. Various in-memory search solutions have emerged to improve the energy efficiency of MANNs. NAND-based multi-bit content addressable memory (MCAM) is a promising option due to its high density and large capacity. Despite its potential, MCAM faces limitations such as a restricted number of word lines, limited quantization levels, and non-ideal effects like varying string currents and bottleneck effects, which lead to significant accuracy drops. To address these issues, we propose several innovative methods. First, the Multi-bit Thermometer Code (MTMC) leverages the extensive capacity of MCAM to enhance vector precision using cumulative encoding rules, thereby mitigating the bottleneck effect. Second, the Asymmetric Vector Similarity Search (AVSS) reduces the precision of the query vector while maintaining that of the support vectors, thereby minimizing the search iterations and improving efficiency in many-class scenarios. Finally, the Hardware-Aware Training (HAT) method optimizes controller training by modeling the hardware characteristics of MCAM, thus enhancing the reliability of the system. Our integrated framework reduces search iterations by up to 32×, and increases overall accuracy by 1.58% to 6.94%.

Metal-ferroelectric-metal (MFM) capacitors with flat amorphous TiN are demonstrated to achieve the c-axis of orthorhombic phase (o-phase) well-aligned along the deposition direction, uniform electric field, negligible fatigue, and a high remanent polarization (2P<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">r</inf>) of 62 μC/cm<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup>. The large lattice misfit between crystalline TiN and HZO creates a larger barrier to form the o-phase HZO as compared to the amorphous TiN underlayer. Using chemical-mechanical polishing (CMP) can obtain a 0.3nm roughness flat TiN, measured by atomic force microscopy (AFM). HZO on flat amorphous TiN exhibits a uniform and record breakdown field <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$(\mathrm{E}_{\text{BD}})$</tex> of 4.8/-5.1 MV/cm for positive/negative voltage. A flat TiN mitigates the formation of oxygen vacancies <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$(\mathrm{V}_{\mathrm{o}})$</tex> as compared to the rough TiN due to the weak and uniform electric field with few local extremes in HZO. After 4E12 endurance cycles, the HZO on the flat TiN exhibits a record final <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$2\mathrm{P}_{\mathrm{r}}$</tex> of 56 μC/cm<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> due to small dipole pinning by <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\mathrm{v}_{\mathrm{o}}{}^{2+}$</tex>. This work demonstrates the way to achieve uniformly high <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$2\mathrm{P}_{\mathrm{r}}$</tex>, large <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\mathrm{E}_{\text{BD}}$</tex>, and high endurance by the flat amorphous TiN.

We present a new selector only memory material, CuGeSe, with low program current, fast switch speed properties and good endurance. The switching mechanism is studied in depth and element migration is verified during the switching of the material. We also discuss application of the material for 3D Xpoint and 3D vertical memory, as well as propose a modified 1/3 V testing scheme for 3D vertical memory to mitigate leakage current and improve scaling.

We present a novel multi-level operation using multi cells on a cross-point OTS-PCM array with no need for program-verify scheme for the first time. This method can provide not only program energy reduction but also low drift property. In addition, a true crossbar array structure is implemented that is ideal for in-memory computing application.

The graph neural network (GNN) has recently become an emerging research topic for processing non-euclidean data structures since the data used in various popular application domains are usually modeled as a graph, such as social networks, recommendation systems, and computer vision. Previous GNN accelerators commonly utilize the hybrid architecture to resolve the issue of “hybrid computing pattern” in GNN training. Nevertheless, the hybrid architecture suffers from poor utilization of hardware resources mainly due to the dynamic workloads between different phases in GNN. To address these issues, existing GNN accelerators adopt a unified structure with numerous processing elements and high bandwidth memory. However, the large amount of data movement between the processor and memory could heavily downgrade the performance of such accelerators in real-world graphs. As a result, the processing-in-memory architecture, such as the ReRAM-based crossbar, becomes a promising solution to reduce the memory overhead of GNN training. In this work, we present the TCAM-GNN, a novel TCAM-based data processing strategy, to enable high-throughput and energy-efficient GNN training over ReRAM-based crossbar architecture. Several hardware co-designed data structures and placement methods are proposed to fully exploit the parallelism in GNN during training. In addition, we propose a dynamic fixed-point formatting approach to resolve the precision issue. An adaptive data reusing policy is also proposed to enhance the data locality of graph features by the bootstrapping batch sampling approach. Overall, TCAM-GNN could enhance computing performance by 4.25× and energy efficiency by 9.11× on average compared to the neural network accelerators.

The aviation industry has a key role in international trade activities. Most studies measure aviation performance based on airlines or airports. However, the frontline operation is delivered via air routes and more operating characteristics can be revealed with route-based performance evaluation. Further, the traditional data envelopment analysis (DEA) approach cannot rank performance in a particular context which represents an efficiency frontier built by decision making units (DMUs). Therefore, this study uses a context-dependent DEA approach to measure and rank the performance of air routes with a case study of 112 international routes from two airlines in Taiwan. Model results identify eight performance levels with most air routes at efficiency performance level 2 and level 3 and most route destinations in East Asia (e.g., Japan). The results of this study can inform operators about a clear relationship between performance and potential markets as well as improvement strategies.