Mitel (United Kingdom)

This work describes how rules for optical proximity correction, derived from lithography simulation, can be favorably changed to improve process latitudes through a metric called a dense-isolated focus/exposure matrix. Example calculations are given to demonstrate the derivation of amended rules.

Optical proximity correction in terms of linewidth correction at different pitches is used to demonstrate improvement in critical dimension control at the polysilicon layer of a sub- half-micron CMOS process. Further measurements across the image field show the effect on wafer linewidth distributions of different generations of the laser write tool used in reticle manufacturing.

A new high performance silicon complementary bipolar technology is introduced. In addition a novel process 'enhancement' technique based on a local oxidation is described and demonstrated and NPN devices with cut-off frequencies up to 45GHz and PNP devices of 20GHz have been fabricate. We propose that the technique we have used will allow specific transistors within a circuit to be optimized, as required.

In this paper, we demonstrate the importance of the interaction between layout and process in reducing the impact of RIE plasma damage. We show that less than optimum layout and a less than optimum process sequence can lead to very severe degradation of device characteristics due to plasma damage, resulting in near zero yielding wafers. Measurements on test transistors can replicate the damage caused and lead to a means of controlling the damage.

A new analytical approach to the low frequency noise analysis in MOSFETs has been developed. Local levels contributing to generation-recombination noise are classified into three groups. For deep levels located near the midgap the approach of zero free carrier concentration inside the space charge region can be used. Simple analytical expressions and conditions of their applicability are derived. Parameters of levels located near the conduction and valence bands can be determined analytically. Analytical expressions for such a situation are also derived. For the intermediate case the level parameters can be only determined numerically. The low frequency noise in n- and p-MOSFETs has been studied experimentally at 220 K < T < 425 K over frequency range 2 Hz < f < Hz. Experimental noise spectra are analysed on the basis of developed theoretical model.

A novel concept for achievement of superior performance in modern fast power diodes is presented in this paper. The junction charge extraction diode (JCE) is based on the integration of low and high lifetime regions in a single structure using masked helium irradiation. This new technique enables us to achieve improved static and dynamic characteristics when compared to uniform and axial lifetime controlled diodes. Simulation and experimental results are presented in this paper to verify the new concept.