National Microelectronics Applications Centre (Ireland)

We present an open-source calibration methodology for Sky130 CMOS at $\mathbf{4 ~ K}$, focusing on robust initial extraction of threshold voltage (VTH0) and slope factor (n) via the SEKVE parameter-extraction tool. To address measurement noise, a partial Z-score filter is applied to the raw data, reducing extraction errors from above 10% to under 2%. These refined parameters then feed into an iterative BSIM4 calibration using IceMOS. As a result, the final calibrated Sky130 models achieve an accuracy in the strong inversion region with median error percentages of 9.49% for PMOS and just 1.11% for NMOS. Transconductance $g_{m}$ calibration is similarly precise with median errors of 5.95% and 2.46% for PMOS and NMOS, respectively, in the strong inversion region. By separating the SEKV-E and IceMOS steps yet integrating them into a fully open-source flow (including Docker-based ngspice simulations), our approach significantly minimizes manual intervention. The Sky130-compatible IceMOS scripts, Z-score routines, and calibrated device models are publicly available, reinforcing the open-source ecosystem for Cryo-CMOS research.

The comparator is a vital block in any integrated DC-DC power converter for both control and protection functions. Monolithic GaN HEMT power converters offer superior power switching performance with lower on-resistances and capacitances, however they suffer from poor analog performance due to their lack of complementary devices and poor device mismatch as well as a limited range of devices. This paper presents the design of a depletion-mode input pair based regenerative comparator monolithically integrated on a GaN-on-Si process. This paper aims to investigate and demonstrate the input-referred offset performance of such a comparator. The structure delivers a transistor level simulated 1-σ input-referred offset of 3.6 mV without the use of any offset cancellation techniques. It achieves rising and falling propagation delays of 29 ns and 22 ns, respectively with a 100 mV overdrive and 1 pF load capacitance. The comparator occupies an area of approximately 0.055 mm<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and has a quiescent current consumption of 63 μA.

This work presents the design considerations of printed circuit board (PCB) and temperature sensing for cryogenic CMOS (Cryo-CMOS) applications. The PCB operates as expected at cryogenic temperatures showing that its structural design and selected materials build a useful support for using it in Cryo-CMOS. The PCB structure includes a thermal bridge made of oxygen-free high conductivity (OFHC) copper, which has demonstrated high efficiency in thermal transfer. For measuring the temperature of the surface of interest a commercial PT100 temperature sensor was used. The electrical test of an on-chip poly-silicon (poly) resistor is assessed for their possible use as a temperature sensor. From experimental results both, the PT100 and poly-resistor, present a residual resistance that was subtracted from the temperature-dependent resistance model in order to know the resistance value at 4 K. For modeling purposes the PT100 sensor was modeled as a series conection of three resistors by following a piecewise linear approach, while the poly-resistor can be described using a second-order polynomial regression.

Fractional-N PLLs are plagued by spurs that result from interaction between the shaped quantization noise introduced by the controller of the feedback divider and non-linearities in the loop. In addition to fixed spurs associated with the fractional input to the divider controller, fractional-N PLLs can also exhibit (i) fixed spurs, whose positions depend on the initial phase setting, and (ii) moving or “wandering” spurs. These become important in applications such as phased arrays that require phase offsets between multiple PLLs and radar applications where wandering spurs can be wrongly interpreted as targets. The divider controller in a fractional-N PLL is commonly implemented as a digital delta-sigma modulator (DΔΣM). The principal source of non-linearity is a time-interval measurement subsystem (TIMS), whose output is a measure of the time interval between the edges of the reference and feedback-divider signals. In a charge-pump (CP) PLL (CP-PLL), the TIMS comprises a phase frequency detector (PFD) and a CP and is typically characterized by a smooth non-linearity. In an all-digital PLL (ADPLL), the TIMS is usually a time-to-digital converter (TDC) that introduces a quantization non-linearity. In bangbang (BB) BB PLLs, the ref and div edges are usually brought into closer alignment using a multibit digital-to-time converter (DTC) before measuring the difference between them. The DTC introduces an additional quantization mismatch and other non-linearities.

In this paper, we propose a digital-to-time conversion (DTC) technique operating entirely in the sinusiodal waveform voltage domain of a crystal oscillator (XO) before the signal's final slicing into the time-domain of the programmably delayed clock, with a deterministic predistortion to further improve the linearity. Precise timing delay is obtained by simply adjusting the dc offset of the sine signal. The technique merges the functionality of DTC with XO generation, thus drastically reducing the power consumption, while offering wide range with fine resolution, low noise and high linearity. Fabricated in 22-nm FD-SOI CMOS, the prototype of XO+DTC consumes only 0.52 mW while achieving a 546 ps range with fine resolution of 266 fs. The rms jitter is only 86.6 fs at a frequency of 100 MHz.

This article presents a millimeter-wave (mmW) frequency synthesizer based on a new charge-sharing locking (CSL) technique. A charge-preset capacitor is introduced for charge sharing with a resonant <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">LC</i> -tank for phase correction, while the resulting charge residue on the sharing capacitor is processed by a digital frequency-tracking loop (FTL) against the process, voltage, and temperature (PVT) variations. Furthermore, a general phase noise (PN) theory of CSL, with injection locking (IL) being a special case, is proposed based on a unified multirate <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${z}$ </tex-math></inline-formula> -domain model, supporting any frequency division ratio <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${N}$ </tex-math></inline-formula> and CSL (or IL) strength <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\beta $ </tex-math></inline-formula> . The new theory sheds light not only on all IL-like PN phenomena (chiefly, its "loop" bandwidth being up to half of the reference frequency, and the oscillator PN increasing 3 dB beyond the "loop" cutoff frequency) but also on how to choose the CSL bandwidth via the sharing capacitor in order to optimize the rms jitter performance. The prototype in 28-nm CMOS achieves 77-fs rms jitter in 21.75—26.25 GHz while consuming 16.5 mW for mmW quadrature frequency generation.

SummaryFlicker noise and white noise from the charge pump (CP) within a phase locked loop (PLL) are key contributors to the close‐in phase noise floor of a fractional‐N frequency synthesizer. The pulse train from the phase frequency detector imposes different types of random pulse modulation on the up and down current sources, which causes different modulation effects to the flicker and white noises at low frequency. This paper rigorously analyzes the underlying noise random modulation mechanisms for the system operating in integer‐N and fractional‐N modes. Transient noise simulation using Verilog‐A behavioral modeling followed by power spectrum analysis is applied to support the mathematical analysis of the random noise modulation.

In this paper, a wideband low-noise amplifier (LNA) with a two-fold noise cancellation scheme is proposed. Finetuned for advanced CMOS, the proposed LNA architecture uses a common-gate input branch to provide wideband input matching. It is followed by two stages of the common-source structure which cancels the noise and distortion of the first and second stages and relaxes the design restriction on the first noise-cancellation stage. The provided circuit-level analysis is verified by simulations. The proposed LNA is fabricated in 28-nm CMOS. It achieves a minimum noise figure (NF) of 2.5dB and input return loss (S₁₁) &#x003C; &#x2212;15dB over 0.02&#x2013;2GHz bandwidth while consuming only 4.1mW from a 1V supply and driving an external 50-<inline-formula> <tex-math notation="LaTeX">$\Omega $ </tex-math></inline-formula> load. The &#x2212;3dB power gain (S₂₁) is 18.5dB and IIP3 is &#x002B;4.25dBm.

Digital delta-sigma modulators (DDSMs) are finite state machines; their spectra are characterized by strong periodic tones (so-called spurs) when they cycle repeatedly in time through a small number of states. This can happen for a range of constant and periodic inputs. Pseudorandom dither generators are widely used to break up periodic cycles in DDSMs in order to eliminate spurs produced by underlying periodic behavior. Unfortunately, pseudorandom dither signals are themselves periodic and therefore can produce spurs in the output spectrum. We call pseudorandom dithering effective if it breaks up periodic cycles in the modulator without producing its own spurs in the output spectrum. This paper presents rigorous mathematical analysis and a design methodology to achieve effective dithering.

Numerous circuit topologies have been proposed for divide-by- injection-locked frequency dividers (ILFDs), most of which have been optimized for division by even numbers, especially divide-by-2. It...