Netcope Technologies (Czechia)

Emerging quantum computing brings many benefits in numerous applications and services as solving efficiently complex operations and problems. Nevertheless, quantum computing may also jeopardize current cryptography standard schemes by solving the problems used in these schemes. Therefore, new quantum-resistant cryptographic primitives and installations are required for the near future. In this work, we present a hardware-based cryptographic accelerator that provides resistance to quantum computer attacks. Directly in VHDL, we design and implement essential cryptographic functions which can be loaded to our accelerator equipped with the FPGA board. Our solution provides efficient encryption, signing, and hashing operations for securing the input data or network packets. Moreover, we create a high-level software demonstrator for setting and using these operations in the accelerator. The presented results prove that cryptography functions accelerated in our hardware-based solution are more efficient than software implementations. Therefore, our solution can provide high-speed and quantum-secure data processing.

We present the architecture and implementation of our encryption system designed for 200 Gbps FPGA (Field Programmable Gate Array) network cards utilizing the IPsec (IP security) protocol. To our knowledge, our hardware encryption system is the first that is able to encrypt network traffic at the full link speed of 200 Gbps using a proven algorithm in a secure mode of operation, on a network device that is already available on the market. Our implementation is based on the AES (Advanced Encryption Standard) encryption algorithm and the GCM (Galois Counter Mode) mode of operation, therefore it provides both encryption and authentication of transferred data. The design is modular and the AES can be easily substituted or extended by other ciphers. We present the full description of the architecture of our scheme, the VHDL (VHSIC Hardware Description Language) simulation results and the results of the practical implementation on the NFB-200G2QL network cards based on the Xilinx Virtex UltraScale+ chip. We also present the integration of the encryption core with the IPsec subsystem so that the resulting implementation is interoperable with other systems.