Onto Innovation (United States)

Advanced semiconductor devices are moving toward three-dimensional (3D) geometries due to scaling demands and performance requirements. Non-destructive metrology necessary for process control of 3D structures must be advanced to facilitate their transition from technology development to high-volume manufacturing. Thin film metrology using Mueller matrix spectroscopic ellipsometry (MMSE) and X-ray diffraction (XRD) film metrology, as well as patterned structure metrology using optical critical dimension (OCD) and X-ray fluorescence (XRF) techniques, have proved capable of measuring the Si∕Si 1−x Ge x superlattices and gate-all-around transistor test structures. Because these techniques are indirect, their limitations associated with superlattice device structures need to be further understood. To understand these limitations, a four-superlattice layer Si∕Si 1−x Ge x structure was measured at four process steps: as an unpatterned film stack, after anisotropic column etch, and at low and high levels of cavity etch. Thin film samples were analyzed with XRD and MMSE, and patterned samples were analyzed using OCD, as well as XRF. A model was developed describing the primary and secondary process effects on the structure. This was evaluated for consistency on datasets collected at different measurement azimuth angles. Square error-based methods were evaluated to quantify OCD model detectability of fit variable step deviations, as well as sensitivity relative to the model to measurement error. OCD and XRF results were compared with reference scanning transmission electron microscopy (STEM) images of nanowire test structure lamellae. Dual-azimuth fit OCD models were found to be within 0.3 nm of the STEM reference mean.

The adoption of tier stacking (dual deck) leads to increasingly high aspect ratios and poses challenges in controlling overlay, tilt, and misalignment in the manufacturing processes for next generation 3D NAND devices. In this work we address metrology challenges such as tilt and overlay separation, measurement robustness influenced by process variation, and nonlinearity of spectral response to asymmetries. We show that Mueller measurement can separate overlay and tilt signals through distinct spectral response analyzed by a machine learning method with reference data. To reduce asymmetry measurement errors caused by process variation such as critical dimension (CD) and thickness changes, we propose and demonstrate improvement of tilt measurements on blind test wafers by feeding forward CD measurement results to the analysis of tilt signal. We also investigate nonlinear regression and show its capability to extend overlay measurement limit from linear response range, ±0.25pitch, to ±0.43pitch. In addition, for small structural asymmetries introduced by channel hole tilt, test RMSE is reduced by 20–40% from nonlinear regression alone or combined with CD feed-forward. We demonstrate that spectroscopic Mueller matrix measurements, paired with advanced machine learning analysis, provide nondestructive and accurate measurement of tilt, overlay, and misalignment for 3D NAND devices with high throughput and fast recipe creation.

Thermal management is a critical aspect of integrated device design and manufacture. Time Domain Thermoreflectance (TDTR) is a powerful tool for the characterization of thermal transport in thin films and multi-layer stacks. In this paper, we present successful extension of in-line non-contact, non-destructive picosecond ultrasonic metrology for simultaneous measurements of layer thickness and thermal properties.

The growing demand for heterogeneous integration is driven by the 5G market. This includes smartphones, data centers, servers, high-performance computing (HPC), artificial intelligence (AI) and internet of things (IoT) applications. Next-generation packaging technologies require tighter overlay to accommodate larger package sizes with fine-pitch chip interconnects on large-format flexible panels. Heterogeneous integration enables device performance gains by combining multiple silicon nodes and designs inside one package. The package size is expected to grow significantly, increasing to 75mm x 75mm and 150mm x 150mm, within the next few years. For these requirements, an extremely large exposure field fine-resolution lithography solution was proposed to enable packages well over 250mm x 250mm without the need for image stitching, while exceeding the overlay and critical uniformity requirements for these packages.One of the challenges of extremely large exposure field fine-resolution lithography is to achieve an aggressive overlay number. Formation changes experienced by the panel as a result of thermo, high-pressure and other fan-out processes shift the design location from nominal coordinates; this causes inaccurate overlay and low-overlay yield in the lithography process. Addressing this critical lithography challenge becomes an important task in heterogeneous integration.In this paper, a 515mm x 510mm Ajinomoto build-up film (ABF)+copper clad laminate (CCL) substrate is selected as the test vehicle. We will analyze the pattern distortion of an ABF+CCL substrate to understand the distribution of translation, rotation, scale, magnification, trap, orthogonality and other errors in the substrate, and then use extremely large exposure field fine-resolution lithography to address the pattern distortion of the substrate. This demonstration will provide an analysis of panel distortion and detail how the extremely large exposure field fine-resolution lithography solution addresses panel distortion to achieve an aggressive overlay number.

Monitoring the high aspect ratio etch profiles in state-of-the-art three-dimensional NAND memory fabrication processes has pushed metrology technologies to new limits. Here, we discuss how a mid-infrared ellipsometric measurement can yield angstrom level discrimination in critical dimension changes of memory channel hole (CH) profiles across such a memory chip. Using finite-difference time-domain and rigorous coupled-wave analysis simulations, we demonstrate how dispersion mitigated mid-infrared beam penetration into these memory structures permits parameter decorrelation and the measurement of the full CH profile.

Few in history have had as great an impact on their field of study than James C. Wyant. This paper provides an historical overview of Wyant’s contributions to the field of optical metrology and how they have impacted today’s technology. Beyond his role as an innovator, inventor, leader, enterpreneur and philanthropist he will perhaps be best known for his teaching and the legacy of the multitudes of students he taught over his career.

Hydrogenated amorphous dielectric thin films are critical materials in a wide array of technologies. In this work, we present a thorough investigation of the thermal conductivity of hydrogenated amorphous silicon nitride $(a\text{\ensuremath{-}}{\mathrm{SiN}}_{x}:\mathrm{H})$, a ubiquitously used material in which the stoichiometry plays a direct role in its functionality and application. In particular, through chemical, vibrational, and structural analysis in tandem with thermal conductivity measurements on chemically variant silicon nitride films, we show that hydrogen incorporation into silicon nitride disrupts the bonding among silicon and nitrogen atoms, and directly impacts the thermal conductivity, leading to as much as a factor of 2.5 variation in heat transfer. This variability, driven by the change in hydrogen content, is fundamentally related to the changes in the average atomic distances, as we experimentally measure with selected-area electron diffraction and computationally show with molecular dynamics simulations. This, combined with our evidence of chemical and spatial fluctuations on the order of average atomic pair distances, leads us to conclude that the vibrational heat transport in $a\text{\ensuremath{-}}{\mathrm{SiN}}_{x}:\mathrm{H}$ is primarily dominated by diffusonlike modes. The results presented in this work combined with our extensive review of prior reports on the thermal conductivity of $a\text{\ensuremath{-}}{\mathrm{SiN}}_{x}:\mathrm{H}$ films resolves discrepancies in decades of prior literature and facilitates a more universal understanding of the vibrational heat transport processes in hydrogenated amorphous silicon nitride.

Amorphous carbon (a-C) based hard masks provide superior etch selectivity, chemical inertness, are mechanically strong, and have been used for etching deep, high aspect ratio features that conventional photoresists cannot withstand. Picosecond Ultrasonic Technology (PULSE™ Technology) has been widely used in thin metal film metrology because of its unique advantages, such as being a rapid, non-contact, non-destructive technology and its capabilities for simultaneous multiple layer measurement [1]. Simultaneous measurement of velocity and thickness for transparent and semi-transparent films offers a lot of potential for not only monitoring the process but offers insight into the device performance. In this paper, we show successful applications of Picosecond Ultrasonics in 3D NAND. This includes measurement of various thin metal films and simultaneous measurement of sound velocity and thickness for amorphous carbon films which has been widely used as hard mask materials.

Fan-out wafer level packaging (FOWLP) is a popular new packaging technology that allows the user to increase I/O in a smaller IC size than fan-in wafer level packaging. Market drivers such as 5G, IoT, mobile and AI will all use this technology. According to Yole Developpement’s analysis, the fan-out packaging market size will increase to $3 billion in 2022 from $2.44 hundred million in 2014, validating the market requirement for fan out packaging. While FOWLP has been used for many years, there is still a relentless drive to reduce the cost, and fan-out panel level packaging (FOPLP) has been proposed as one possible solution. FOPLP allows users to put more chips on a substrate, meaning more product output and a higher substrate utilization percentage. According to Yole’s analysis, the FOPLP market size will increase to $2.79 hundred million with 79% CAGR, showing that more people are adopting FOPLP.FOPLP has many advantages and low cost potential, but it faces significant process challenges, such as die placement error and substrate warpage control. One of the key challenges is the trade-off between overlay, yield, and throughput during the lithography processing steps. A user exposes multiple dies per exposure shot to increase throughput, but this can result in lower overlay yield because of pick and place die placement error. To overcome the low yield issue, each die needs to be aligned, but this impacts throughput, so a compromise is required. To find the balance point between throughput and overlay is one of the biggest challenges for FOPLP.In this paper we address the tradeoff between throughputs and overlay yield, we demonstrate an integrated feedforward adaptive shot solution. This feedforward approach uses a third party metrology system to measure reconstituted panel die location data and sends the data to the stepper via a network. With feedforward algorithm technology, the stepper uses smart adaptive shot technology to generate an optimized variable shot size layout. This layout ensures the overlay yield is within specification with the minimum number of exposure steps. With feedforward adaptive shot technology, the user can maximize the throughput of the stepper and ensure the overlay yield at the same time.