Osemi (Canada)

Traditionally, we define a safe operating region for flip-flops using the setup and hold time constraints, with other timing attributes, such as clock-to-Q (C2Q) delay, modelled with the assumption that the flip-flop operates within this region. However, in reality, these constraints and C2Q delay are interdependent, and a conservative approach is taken to define these constraints. Hence, traditional flip-flop models, though safe, hinder optimization and limit overall performance improvement. In this paper, we leverage machine learning (ML) techniques to define a safe operating region for a flip-flop, effectively extending the traditional timing space. Specifically, rather than modelling setup and hold times, we develop an ML model that predicts the probability of latching data correctly by a flip-flop. This model considers the overall impact of circuit conditions, such as setup and hold skews, and also accounts for process-induced variations, thus implicitly capturing the dependencies among various parameters missing in the traditional model. Additionally, we propose a second ML-based model to accurately predict the C2Q delay within the extended timing space. Furthermore, we demonstrate the application of these models in resolving marginal timing violations through waivers rather than implementing design modifications. We propose a hierarchical violation waiver framework that enables safely waiving violations. Besides considering latching probability, the violation waiver checks that the timing space extension does not introduce issues for flip-flops that were already operating safely under the timing constraints of the traditional model. We validate the proposed framework on TAU CONTEST’19 benchmark circuits, implemented with 45 nm technology libraries and verified against Monte Carlo SPICE simulations. Results show that marginal violations are effectively filtered with a precision of 100% (i.e., avoiding false positives) and errors in computing C2Q delay are less than 2% compared to the golden SPICE delay computed in the extended timing region.

Integrated circuits used in modern, digital hearing aids are mixed-signal devices that combine analog and digital circuits on the same die. Due to the extreme size and power constraints encountered in hearing aids, the assignment of die area for such systems-on-chip (SOCs) must be carefully considered. The relative allocation between analog circuits, digital gates and on-chip memory has been relatively constant for traditional DSP-based systems. The precision and computational requirements for artificial intelligence (AI) based algorithms, however, are very different from traditional DSP. This is driving changes in die area allocation, starting with some recently launched devices. Despite these changes, projections based on recent growth trends show that future SOCs will only be able to support the smallest neural networks currently proposed for hearing aids. Minimizing data precision and pruning small-valued weights are shown to be essential to deploy deep-learning algorithms on hearing aid SOCs.

In this paper, the authors continue the experimental evaluation of bipolar degradation for different 1.2 kV SiC MOSFETs. All the devices are stressed by pulsed repetitive forward current through the body diode with current densities varying from 1000 A/cm2 up to 5000A/cm2. The 1.2 kV SiC MOSFETs are split into two major groups based on the differences in epitaxial material (Type A and Type B) that are subjected to the pulsed forward current stress through the body diode. Additionally, there is a third group with Type B epitaxial material, where p+ implantation process at different temperature is applied to evaluate potential impact on bipolar degradation. Devices are electrically characterized on the Keysight B1505A power device analyzer, both before and after stress testing to trace the drift in the electric parameters. Lastly, the drift in parameters observed in some of the devices, are additionally correlated by an electroluminescence (EL) and scanning acoustic tomography (SAT) analysis.

We have investigated carbon behavior resulting from pressure control in furnace thermal oxidation process and evaluated the effect on gate oxide quality resulting from this pressure control. In order to investigate the potential reduction of carbon defects by reducing CO and CO2, an analysis of oxidized SiC wafers was conducted. To evaluate the effect of pressure control related carbon component change during thermal oxidation, QBD characteristic was evaluated in SiC MOS Capacitance. The analysis results revealed on observable decrease in carbon at the SiO2/SiC interface and the SiO2 layer. The QBD results shown that improved at lower pressure better than those obtained in the general pressure.

Silicon Carbide is rapidly growing in the power electronics industry. This is fueled to a great degree by the adoption of electric cars and power electronics needed both inside the vehicle and to support the charging infrastructure. This attention from automotive industry comes with a clear spotlight on the cost, quality, and efficiency of SiC power devices. This in turn results in intense pressure and scrutiny to improve yields and reduce defects in every part of the manufacturing chain. There is a wide release and proliferation of Diode and MOSFET devices from various companies in the marketplace. Several companies are investing billions of dollars in capacity expansions driving exponential growth of wafers and devices.In this review, we will discuss the steps and processes of fabricating a SiC wafer including crystal growth, wafering, epitaxy and device fabrication. The process challenges associated with the steps unique to SiC will be highlighted with a perspective on scaling up volumes and the transition to 200mm wafers. New innovations at some of the steps are enabling higher efficiency and output. The impact of these innovations will be presented. In addition, defects at each step of the process will be reviewed along with how they interact with the following steps [1]. Finally, the effect of various processes and defects on devices and reliability will be presented [2,3].