PREtest Consult (United States)

Considerando a universalidade proporcionada pela educação a distância, bem como, devido a necessidade de atrelar teoria à prática, especialmente no que tange aos cursos Tecnólogos voltados ao mercado de trabalho e as novas tendências advindas com os cursos experimentais da área jurídica é que se propôs o desenvolvimento de um Projeto de Ensino voltado ao desenvolvimento das práticas de negociação com as técnicas de Harvard.

The overall objective of this study was to evaluate the influence of selected recycling agents (RAs) and recycled materials on the development of cracking potential with respect to oxidative aging. Given the complex nature of varying base asphalt binders, recycled materials, whether recycled asphalt pavement (RAP), reclaimed asphalt shingles (RAS), or both, and the complexity of their combined interactions with recycling agents, standard evaluation protocols for binder grading and evaluation may be insufficient. The binder blend aging predictions or oxidation modeling evaluation was introduced as a means to evaluate the combined influence of both binder oxidation kinetics and resulting rheological changes on the measured cracking potential of the various binder blends—that is, Glover–Rowe (G-R) parameter—driven by temperature estimation modeling over simulated in-service durations at example geographic locations. This evaluation has demonstrated the importance of adequate characterization of the specific materials being used in conjunction with selection of the correct dose of the appropriate recycling agent to ensure sufficient resistance to cracking and embrittlement of proposed material combinations. The combined influence of all the interested components did not always add up to the sum of the individual parts, nor are the measured interactions consistent with increased levels of oxidation. Therefore, the prevailing conclusion of the study as a whole indicated that material-specific evaluations are needed to identify the complex interactions taking place within the material combinations of interest, but also multiple levels of aging at appropriate intervals may be necessary for comprehensive characterization.

Digitale Technologien durchdringen zunehmend fast alle Lebensbereiche. Fur die gesellschaftliche und wirtschaftliche Entwicklung Deutschlands sind damit bestimmte Risiken, insbesondere aber auch enorme Chancen verbunden. Nicht nur das weitere wirtschaftliche Wachstum, sondern auch eine positive gesellschaftliche Entwicklung sind eng mit der zukunftigen Ausgestaltung der „Digitalen Gesellschaft“ verknupft.

The Hartsfield-Jackson Atlanta International Airport opened a critical end-around taxiway in April 2007 to reduce operational delays for air and ground traffic. As part of the construction specifications, the Contractor was required to prepare three feet of soil subgrade by undercutting and recompacting in order to achieve a minimum design modulus of subgrade reaction (k-value) of 90 pci. A value engineering alternative was utilized to verify the capacity of in-situ soils using a portable, light weight deflectometer (LWD) and laboratory resilient modulus tests to model the pavement subgrade modulus. A validation of direct k-value (from LWD testing) was performed by comparing to the k-value obtained from resilient modulus testing. The final phase of the test program involved the computation of in-situ subgrade modulus from LWD for the remaining part of the Taxiway Victor to demonstrate the suitability of in-situ soils thus eliminating majority of the traditional subgrade preparation, as specified originally in project documents. The LWD offered an added advantage of fast turn-around results after the collection of field data. The paper provides a background of existing subgrade issues, the test program methodology and conclusions from this value-engineering approach.

Production test and device I/O characterization are different tasks. Measurements and analysis associated with these different tasks need quite different tools. 1 Serial Data Links -the future is “bright” The 2001 ITRS predicted serial datacom rates reaching 40 GBPS by this year, doubling within a decade - and 40 GBPS production devices now exist. A 12.5 ps unit interval is tiny by today’s standards; for reliable data transmission to reach these rates the challenges are daunting. Despite this, we can fully expect such serial data links. What is required for them to be producible? Quite simply: reliable design, consistent process technology, and solid production test capability. 2 Design Qualification vs Production Test It is absolutely necessary to distinguish clearly between design qualification/characterization and the sort of test necessary to guarantee that a particular device is manufactured properly. Yet to sort one from the other is no mean task. It only takes a few extra ohms of interconnect to marginalize a good design; these few extra ohms will displace a transition by a few but unacceptably large number of picoseconds. Each bit in a high-speed serial data stream can be characterized by two key parameters: unit interval and individual edge displacement, expressed as a fraction of unit interval. Edge displacement is often referred to as jitter. Jitter is an unfortunate term, as it masks what is actually going on. Yes, some edges are out of place, but why are they? Displaced edges are created by intersymbol interference, internal systematic path or propagation delay errors, clock phase error, and random noise. These errors must be identified and minimized during the design qualification phase; the design is acceptable if error rate is sufficiently below target unless the product is defective. Key point: “random noise” in semiconductors is not very large. RJ in excess of 1 ps is more likely to be instrumentation noise than true circuit noise, or else is uncorrelated systematic error. This error is likely to be correctable in design. Laboratory equipment is generally capable of acquiring the data necessary to characterize today’s I/O designs. However, it is a costly mistake to attempt to translate these characterization tasks into a production test requirement. Measuring “jitter” in a production test environment is unneeded. What might be measured (and compared to design minimum, nominal, and maximum) are bit-by-bit displacements focused specifically on the structure of the specific serializers or deserializers in the signal path. This requirement is derived from the concept of defect-based testing: each element in the circuit (whether transistor, passive component, or interconnect) has a target quality requirement; if it is not manufactured to this quality requirement then something - something specific - is wrong. Yet this overall approach is insufficient by itself. It misses the tight coupling of the serial data stream to its internal self-aligned clock. If this clock is too erratic, then perfect serializing or deserializing circuitry will break. Conclusion: production test has two requirements: qualify the clock and qualify the bit generators or extractors. There should be no need for long data streams, or concomitant long test times.

ICs developed for data communications present a number of challenges in the development of test solutions to be used in validation, characterization, and high volume production. One of the most obvious challenges is the frequency and data rates at which these devices operate. The OC-48 standard in use today transmits and receives data at 2.5 Gbps. Emerging standards of "Xaui" and "OC-192" operate at 3.2 Gbps and 9.6 Gbps respectively, which provide even greater challenges. The majority of ATE today operates at /spl Lt/1 Gbps. A few ATE companies have announced solutions that will be able to provide at 3.2 Gbps, but these solutions are hard to find. Other challenges are jitter requirements as low as 5pS, non-deterministic data delays in the devices, signal pin counts above 500 pins, and low voltage differential swings. This paper looks at these challenges and solutions. The results from OC-48, Xaui, and OC-192 projects developed by NPTest SABER will be presented. These solutions use a combination of ATE, external instrumentation, custom interfacing, and software. The paper will also look at tradeoffs in these solutions.

This paper reports on an investigation of optical waveform signatures available from PICA. PICA collects photon emission data in time and space (t, x, y) simultaneously from all transistors in its 160 /spl mu/m field of view. This data if consistent can be used to determine process uniformity, non-catastrophic failures and degradation of transistors during reliability testing by comparing transistor optical waveform signatures. As PICA is essentially a remote sensing technique it may predict failures early-on and thus accelerate reliability testing. Therefore, we have also investigated to see if this is observed.

Using a focused ion beam (FIB), secondary electron (SE) imaging of n-wells under oxide from the backside of thinned integrated circuits without electrical bias was accomplished. From the backside, the n-wells were initially observed at a remaining silicon thickness ∼4.5μm, which correlates to the actual implant depth where n and p carrier concentrations are equal. When the wells were FIB imaged, contrast appeared dark relative to the p substrate. During deposition of the oxide film, the n-well brightness changed from dark relative to the p-substrate, to bright. It appears that initially during this deposition step the interaction volume of the beam reached the silicon/oxide interface to create tunneling electrons. This phenomenon dominated the capacitive effect. Then as the film thickness increased the capacitive effect prevailed. The imaging structure is analogous to a Metal-Oxide-Semiconductor (MOS) capacitor. The n- and p-MOS capacitive properties yielded a permanent imaging contrast. At an optimized oxide thickness (130nm), the n-wells appear white relative to the p-substrate with a contrast up to 85% {(Ip-substrate − In-wells)/(Ipsubstrate + In-wells)}.

Accurate deflection readings must be obtained when using NDT devices in order to obtain correct backcalculated layer moduli. This paper provides an analysis of the sources of deflection errors and illustrates through a series of examples how random deflection errors and random pavement thickness errors affect backcalculated moduli. The consequence of these errors is most pronounced in the backcalculated modulus of the surface course. The moduli of the base and subbase layers are also affected, and the subgrade moduli are only slightly affected by these errors. To some degree this outcome may be due to the bottom-to-top approach used by the backcalculation program MODCOMP 2. The consequence of the variability of the backcalculated moduli on the required pavement overlay thicknesses was found to be minimal. This was due to the fact that, generally speaking, data errors which cause an overestimate of the base course modulus also cause an approximately equally significant, but opposite, underestimation of the surface course modulus. Thus, the needed overlay requirement remains nearly the same. The paper shows how certain FWD calibration and testing procedures can be used to minimize deflection measurement errors. The accuracy of backcalculated moduli is shown to be determinable from the RMS error of the deflection fit. The examples provide an impression of the extent to which random layer thickness errors and deflection measurement errors will influence the ability to discern point-to-point variability of layer moduli for the specific pavement structure considered in this investigation. This provides a perspective from which the practical accuracy of the backcalculation approach can be judged.