Photronics (United States)

The rapid development of the Internet of Things (IoT) and smart industrial systems has created an urgent demand for high-performance gas sensors capable of room-temperature operation with low power consumption. To date, while field-effect transistor (FET) architectures have demonstrated remarkable capabilities in addressing key challenges related to miniaturization, power consumption, and sensitivity, the conventional designs' critical dependence on channel materials for selectivity and stability imposes stringent selection criteria, which significantly limits their application scope. Here, we report an atomically thin all-2D gate-sensitive field-effect transistor (GS-FET) based on an h-BN/MoS2 heterostructure. This design decouples the functions of chemical recognition and charge transport, which not only ensures the stability of the channel material but also allows for flexible tuning of selectivity. Moreover, the atomically thin architecture enables ultrasensitive detection capabilities. Devices with two distinct floating-gate materials (1 nm-thick Ni5Pd95 alloy and Pt) were fabricated, and combined DFT calculations and experimental measurements demonstrate that Ni5Pd95-based and Pt-based devices are optimized for high sensitivity (0.056%/ppm) and fast response/recovery kinetics, respectively. Systematic studies reveal that the thickness-dependent capacitive coupling of the h-BN dielectric provides an additional degree of freedom for sensitivity tuning, while its atomically flat interface minimizes charge scattering and enhances carrier mobility. Furthermore, the h-BN-encapsulated device exhibits superior humidity resistance and long-term stability. This work establishes a universal materials platform for gas sensing that combines the exceptional properties of 2D materials with unique device architecture, opening new possibilities for high-performance environmental monitors, industrial safety systems, and wearable health diagnostics.

Abstract Improving the landslide risk prevention by defining the risk of slope deformation in geological environment prone to mass movements within the Slovak Republic, is the primary objective of the geological task Identification, Inventory and Engineering Geological Mapping of Slope Deformations which was solved in 2018–2023. It concerns the exploration of 5 regions significantly threatened by slope failures with a total mapped area of approximately 3,195 square kilometres. One of these regions are Biele Karpaty Mts. with an area of 606.4 km2. The inventory itself was preceded by the creation of a detailed digital terrain model (DTM) generated from airborne LiDAR data. Engineering geological and geological mapping was aimed at refining the position of the covering Quaternary lithological complexes and the slope deformations and other geohazards using precise DTM and GNSS technologies. This was followed by the updating the database of slope deformations operated by SGIDŠ and by the preparation and creation of parametric maps necessary for the development of the landslide hazard forecast by numerical methods in the GIS environment. In this paper we present results of the mapping and their comparison with existing Atlas of Slope Stability of the Slovak Republic.As a result of mapping in the region of the Biele Karpaty Mts., 2,951 landslides covering the total area 109.6 km2 were registered. A differentials map of landslide near Machnáč Hill was created by using interpolated LiDAR data comparison of the two differential digital terrain models (2018 vs 2021) via map algebra analysis.

In distributed generation (DG) systems, grid-tied inverters commonly adopt multi-mode control strategies to achieve operational objectives under different operating conditions. Therefore, achieving seamless mode transition between grid-connected and off-grid modes without excessive overcurrent and circulating current is of critical importance. This paper proposes a novel seamless transition control strategy for a master-slave parallel system by utilizing phase-locked loop (PLL) and phase synchronization control loop (PSCL) that only operate in the master inverter, combined with CAN communication and appropriate time delay, it achieves simultaneous switching of master and slave inverters. The control structures in different modes are presented, and the operational principles of proposed transition control strategy is analyzed in detail. Finally, the control scheme is validated on an experimental master-slave parallel system.

<div class="section abstract"><div class="htmlview paragraph">Current hybrid and electric powertrains in Class 1 through to Class 7 vehicle segments, are still disadvantaged by very low market penetration due to high procurement and operational cost barriers which have increased the gap between the technology experience and the expected benefits of powertrain electrification.</div><div class="htmlview paragraph">Fundamentally, baseline gasoline and diesel vehicles with over 100 years of established supply chain network and manufacturing economies of scale, have made it difficult for hybrid and electric alternatives to compete even with the continuous drop in price of these new technologies and numerous government incentives.</div><div class="htmlview paragraph">A new approach is proposed in this segment with an Integrated Torque Assist Transmission (ITAT) that addresses the typical fuel inefficiency challenges of the baseline powertrains where mostly up to 12% of their fuel content is used for actual vehicle propulsion while the rest is lost to heat dissipation. The new ITAT replaces the stock transmission as an electrification upgrade with the choice of a Battery or Ultracap energy storage system of 48V or 300V specification. The transmission system can be retrofitted as an aftermarket upgrade or installed on the assembly line.</div><div class="htmlview paragraph">A model cargo van is used to demonstrate the benefits of the torque assist transmission approach which includes engine downsizing if applicable or better fuel economy from the stock engine if it is retained as well as the cost benefit of over 60% off the shelf component sourcing using most of the existing supply chain and manufacturing infrastructure.</div></div>

Development and manufacturing techniques applied in mask making and wafer lithography have many similarities. Moreover, these disciplines have jointly progressed enabling generations of IC performance advancement. Despite the similarities, there are also fundamental differences in how these two fields have evolved including the driving forces and constraints inherent in each. It is perhaps difficult to fully appreciate these differences unless one has walked a mile in the others shoes so to speak. From how yield and cycle time are characterized to equipment infrastructure and the evolution of performance parameters, we will open a curtain on certain aspects of mask making from an erstwhile lithographer's perspective in hope this can lead to new avenues for mask and lithography co-optimization. In addition, as the industry ramps EUV alongside an expansion in global design activity across all nodes, it is timely to revisit these unique challenges in mask making to assess whether new frameworks might further advance the capability in service to the design and lithography communities.

Design weak points, or “hotspots” remain a leading issue in advanced lithography. These often lead to unexpected critical dimension (CD) behavior, degradation of process window and ultimately impact wafer yield. Industry technology development focus on hotspot detection has included full chip lithography simulation and machine learning-based hotspot analysis. Most recently, the machine learning approach is gaining attention because it is faster and more practical than lithography simulation-based hotspot detection. The machine learning case is a feedback approach based on previous known design hotspots. Conversely, the simulation method has the benefit of proactively detecting hotspots in a new design regardless of historical data. However, full chip simulation requires resources in calculating time, computing power and additional time-to-market that render it impractical in some scenarios. As design rules shrink, advanced mask designs have significantly increased in complexity due to Resolution Enhancement Techniques (RET) such as Source Mask Optimization (SMO), advanced Optical Proximity Correction (OPC) and high transmission attenuating mask films. This complicates hotspot detection by existing OPC verification tools or rigorous lithographic simulation with wafer resist model. These resultant complex mask geometries make OPC optimization and hotspot detection using post design very difficult. In this paper, we will demonstrate the limitation of traditional hotspot detection technology. Typical OPC tools use simple techniques such as single Gaussian approximations on the design, such as corner rounding, to take the mask process impact to the geometry into account. We will introduce a practical lithography hotspot identification method using mask process model. Mask model-based hotspot detection will be used to precisely identify lithography hotspots and will provide the information needed to improve hotspots’ lithographic performance.

Photomasks constitute a critical part of the electronic circuit device manufacturing processes. A photomask morphs into design patterns of devices through a lithographic process. Any defects on a photomask will cause repeating defects in circuits lead to yield loss. However, most of defects generated in mask fabrication processes have been mainly created during each unit process. A different formation mechanism defect which formed between processes to processes was studied in detail and different from previous defects.In this paper, we introduced two different defects formed at mask making stage. The phenomenon was believed the Crosstalk defect between develop to etch process is considered to after develop residue chemical reaction to dry etching plasma component generation ammonium salts as defect source. To recover the defects, the first one used the longer and strong rinse to remove the salt as far as possible and the second one used the optimized etch recipe by change bias power to minimum the formation of salts. The long-term monitor data showed the defects counts could be reduced from hundreds defects to less than 15 counts.

The ongoing trend to smaller structures and an increasing number of high MEEF patterns in mask design makes defect disposition and repair verification more critical than ever. For AIMS™ as the standard method for defect disposition and repair verification, the requirements are getting tighter. Additionally, the efforts required for defect analysis are steadily increasing. As a result, mask manufacturers are forced to continually find methods to increase productivity and optimize the cost of defect disposition. Smart solutions for automated defect treatment together with a high degree of tool integration play an increasing role in this challenge. With AIMS™ AutoAnalysis, which provides fully automated analysis capability of AIMS™ aerial images, ZEISS addresses this challenge. Due to direct connection and communication of AutoAnalysis with the AIMS™ system via the FAVOR® platform, the image analysis process runs in parallel to the measurement process. A high degree of automation reduces the influence of human error and provides highly reliable results. In the following paper a study is presented demonstrating the benefits of the implementation of AutoAnalysis in the production environment at Photronics, Inc. The study was carried out by analyzing defects on pattern sets, varying from simple to very complex patterns. Furthermore, the analysis capabilities of AutoAnalysis have been compared with the capability of operators and engineers. The performance of AutoAnalysis is presented showing significant time saving in the defect disposition process as well as an overall increase in reliability of analysis results.

Semiconductor scaling is slowing down because of difficulties of device manufacturing below logic 7nm node generation. Various lithography candidates which include ArF immersion with resolution enhancement technology (like Inversed Lithography technology), Extreme Ultra Violet lithography and Nano Imprint lithography are being developed to address the situation. In such advanced lithography, shot counts of mask patterns are estimated to increase explosively in critical layers, and then it is hoped that multi beam mask writer (MBMW) is released to handle them within realistic write time. However, ArF immersion technology with multiple patterning will continue to be a mainstream lithography solution for most of the layers. Then, the shot counts in less critical layers are estimated to be stable because of the limitation of resolution in ArF immersion technology. Therefore, single beam mask writer (SBMW) can play an important role for mask production still, relative to MBMW. Also the demand of SBMW seems actually strong for the logic 7nm node. To realize this, we have developed a new SBMW, EBM-9500 for mask fabrication in this generation. A newly introduced electron beam source enables higher current density of 1200A/cm2. Heating effect correction function has also been newly introduced to satisfy the requirements for both pattern accuracy and throughput. In this paper, we will report the configuration and performance of EBM-9500.