Powerchip (Taiwan)

Device shrinkage requires continuous tightening of the overlay (OVL) control. Systematic deviation between optical after-develop inspection (ADI) and after-etch inspection (AEI) OVL, known as non-zero offset (NZO), is critically important when applied to the scanner process. In the 28 nm logic process, the VIA layer relies on accurate OVL control to ensure device yield. In this paper, we discuss in-device SEM-based OVL metrology of the VIA layer to demonstrate the NZO gap and enable a better corrective methodology to minimize NZO in the advanced process control (APC) loop. In addition, the SEM OVL is valuable for providing more detailed and comprehensive OVL distributions, enabling high-order correction of the scanner process.

The two-transistor metal-ferroelectric-metal field-effect transistor (2T-MFMFET), a new back-end-of-line (BEOL) compatible ferroelectric (FE) memory, is recently proposed. 2T-MFMFET is designed to achieve all the critical features of embedded nonvolatile memory (eNVM) at the advanced logic nodes, namely, process compatibility, high retention, excellent endurance, low operating voltage, and superior area scalability. In this study, we detail the operation principles of 2T-MFMFET, including both the memory cell and memory array. Furthermore, a compact model of 2T-MFMFET is developed to evaluate its design space, which shows promise for a low operating voltage of 2 V with a low polarization charge density of less than <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$3~\mu \text{C}$ </tex-math></inline-formula> /cm2. Additionally, 2T-MFMFET shows a 136% improvement in area density compared to the static random access memory and negligible read/write disturbance in the array.

The above article <xref ref-type="bibr" rid="ref1" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">[1]</xref> presented data on microwave annealing of implanted ions in silicon. There are several typos in the figure captions and labels, and the authors would like to correct them. The text is correct, and the conclusion of <xref ref-type="bibr" rid="ref1" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">[1]</xref> is not impacted by these revisions.

This work integrated a 3D high density (HD) and high aspect ratio(>30) cylinder MIM capacitor in Si interposer with 3 to 5 BEoL Cu layers (Min. width/space is <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$0.36/0.36\ \mu\mathrm{m}$</tex> for each layer within 1X Reticle) for 2.5D advanced packaging applications. The characterization of 3D HD capacitor with high capacitance density ( <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$&lt; 18\ \mu\mathrm{F}/\text{mm}^{2}$</tex> ), high distributed compatibility (>40% interposer area), and low leakage ( <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$0.1\ \text{pA}/\mu\mathrm{m}/\text{mm}^{2}$</tex> under 2V at 25°C) is benefit to power integrity design. Comparing to typical integrated passive device (IPD) which is bonded at substrate landside, this work proposed a kind of monolithic 3D HD Capacitor and Si wafer technique. The Si interposer is consisted of through-silicon-via (TSV), fine pitch re-disturbing layer (RDL) and 3D HD capacitor can be a good chip substrate solution for high-performance and high-frequency application in artificial intelligent (AI), high performance computing (HPC), and System in package (SIP) region.

The focus of this study was to investigate the detection of neutralizing antibodies (Nabs) in maternal serum and cord blood as the targeted samples by employing a lateral flow immunoassay combined with a spectrum reader (LFI-SR) and the correlation of Nab protection against different types of SARS-CoV-2. We enrolled 20 pregnant women who were vaccinated with the Moderna (mRNA-1273) vaccine during pregnancy and collected 40 samples during delivery. We used an LFI-SR for the level of spike protein receptor binding domain antibody (SRBD IgG) as Nabs and examined the correlation of the SRBD IgG concentration and Nab inhibition rates (NabIR) via enzyme-linked immunosorbent assays (ELISA). The LFI-SR had high confidence for the SRBD IgG level (p < 0.0001). Better NabIR were found in wild-type SARS-CoV-2 (WT) compared to Delta-type (DT) and Omicron-type (OT). Women with two-dose vaccinations demonstrated greater NabIR than those with a single dose. The cut-off value of the SRBD IgG level by the LFI-SR for NabIR to DT (≥30%; ≥70%) was 60.15 and 150.21 ng/mL for mothers (both p = 0.005), and 156.31 (p = 0.011) and 230.20 ng/mL (p = 0.006) for babies, respectively. An additional vaccine booster may be considered for those mothers with SRBD IgG levels < 60.15 ng/mL, and close protection should be given for those neonates with SRBD IgG levels < 150.21 ng/mL, since there is no available vaccine for them.

Efficiency and operation lifetime of blue triplet‐triplet annihilation organic light emitting diodes (TTA‐OLEDs) were enhanced by 16% and 297%, respectively, by employing double emitting layer structure. Blue OLED with maximum external quantum efficiency of 9.4% and half‐lifetime of 96,620 hours at initial luminance of 1,000 cd/m 2 was achieved.

We fabricated a 1.50‐inch, 3207‐ppi OLED display with drivers capable of 32‐division driving, which is achieved by monolithically stacking OSFETs over SiFETs. Taking advantages of minute OSFETs with a high withstand voltage, Si‐OS connection regions were provided in subpixels to connect Si drivers and OS pixel arrays at given positions.

We demonstrate highly manufacturable, reliable, and energy-efficient SOT-MRAM by developing damage-free reactive-ion etching (RIE) recipes. The experimental results demonstrate that C-F Etch lowers the CoFeB/MgO interfacial anisotropy, partially destroys the magnetic moment of CoFeB, and the post-etch annealing further degrades the magnetic moment. On the other hand, N-H Etch hardly changes the stack magnetic property. The present process technology allows to etch uniformly stop on the thin heavy-metal (HM) layer and resulting in a low SOT-channel resistance <250Ω. A statistical full wafer-level study of the SOT switching properties such as TMR%, SOT-channel resistance, P2AP/AP2P voltages, and P/AP-state resistances has been explored.