PrivaTran (United States)

Oxide based resistive switching memory are the promising candidates for future non-volatile memory according to fast programing, low power operation, scalability and compatibility to the current CMOS process. Among, SiOx single layer resistive switching devices have been widely studied and characterized. The SiOx single layer resistive memory has good compatibility to CMOS fabrication process. However, it can only be programmed under the vacuum or non-oxidized ambient. Also, the previous results reported on SiOx-based memristors indicate that the electroforming and programming voltage is relatively higher than the other dielectric materials and obstructed for low-power applications. In this work, by using SiOx/HfOx stacking engineering, we have developed a low-voltage operation (< 2V) for SiOx-based ReRAM. The results show that with HfOx (3nm) on bottom, the metal-insulator-semiconductor (MIS) structures exhibit resistive switching at low voltage (<2V) and operation in air atmosphere. The added hafnium layer apparently provides the source of proton exchange reaction with conduction bandgap offset reduction for low-voltage (< 2V) RS (Figure 2). Also, we have studied single HfOx-based MIS devices which exhibit bipolar-type resistive switching behaviors with small memory window.Clearly, SiOx/HfOx stacking optimization not only maintains the RS behaviors even in air environment without any programming window degradation, but also further reduces the switching voltage below 2V. Figure 1 shows the results of three different structures, including SiOx single layer memristor, SiOx/HfOx bilayer memristor and HfOx single layer memristor. In terms of operation environment condition, inserting the HfOx layer would help the SiOx memristor to be able to programmed either under a pressure of 1E-4 torr or in the atmosphere. The HfOx single layer memristor has the lowest electroforming voltage of 2.3 V, and which in SiOx/HfOx stacks has been reduced significantly to 5 V comparing which of 14 V for SiOx single layer. For the SiOx/HfOx bilayer, a memory window of 4 decades is achieved and comparable to that of SiOx single layer, and larger than that of single layer HfOx by 2 decades. In terms of operation voltage, the set voltage is reduced from 4V to 2 V and the reset voltage is also suppressed significantly from 10 V to 0.3 V by inserting the 3 nm HfOx layer. Figure 2 shows the TEM images of both SiOx single layer memristor and SiOx/HfOx bilayer memristor. The 3 nm HfOx was deposited on N+ Si wafer at 250 oC by atomic layer deposition followed by 30 nm SiO2 deposition using e-beam evaporator and 160 nm TaN depositing by sputtering. Figure 3. The single layer HfOx-based MIS devices resistive switching behaviors. (a) The electroforming process, resistive switching behaviors in 20 times cycling. (b) The switching voltage (SET/RESET) and states (HRS/LRS) distribution. Figure 1

Vertically aligned carbon nanotube (CNT) arrays can provide the required combination of high thermal conductivity and mechanical compliance for thermal interface applications. Much work in the last 15 years has focused on improving the quality and intrinsic thermal conductivity of the nanotube arrays. Currently the thermal interface resistance between nanotube arrays and surrounding materials limits the overall thermal performance. To reduce this interface resistance, we propose coating the nanotube film with a continuous layer of metal. In this work, we electroplate 1 to 20 μm-thick continuous copper films directly on the carbon nanotube array. We measure the thermal conductivity of CNT arrays after electroplating using cross-sectional infrared microscopy. For low volume fraction, vertically-aligned carbon nanotubes arrays with copper electroplating (0.5 vol. %), the film thermal conductivity is nearly 3 W/m/K. These results demonstrate the feasibility of the electroplating method to coat CNT films.

The resistive switching between high impedance (“off” state) and low impedance (“on” state) is demonstrated on e-beam evaporated SiOx/Si resistive random access memory devices in this paper. The set and reset voltages are independent of the device perimeters and oxide thicknesses after electroforming. A circuit model including filament conductance G is proposed to explain the measured “on” state capacitances under frequency ranges from 1 KHz to 1 MHz. The electrochemical redox process is adopted to explain the formation of Si filament during electroforming and switching. “On” and “off” currents were also measured at various operating temperatures. It is found that both set and reset voltages increase as temperature decreases and that no electroforming is exhibited at low temperature T = 77 K.