- Conference Article
- 10.1109/c2i666499.2025.11366974
Enhanced FIR Filter Architecture for Fast and Efficient DSP Implementation
- Dec 05, 2025
- B Bharatha + 4 more +4
A high-performance arithmetic architecture is introduced for digital signal processing systems in biomedical, imaging, and embedded domains. The architecture combines Booth’s algorithm, Wallace Tree multiplication, modified carry logic, and a square root carry select adder, with parallel FIR filtering to reduce latency and improve throughput. Static timing analysis shows improvement in worst negative slack from minus $\mathbf{- 0. 7 0 6 ~ n s}$ to $\mathbf{+ 3. 6 5 1 ~ n s}$. Total negative slack was eliminated, and pulse width slack increased by 52.9%. The design achieves up to 40% reduction in computation time, with improved power and area efficiency under timing constraints. Index Terms-Finite Impulse Response (FIR) filter, squrae root carry select adder (square root CSLA) Digital Signal Processing (DSP).
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