Realtek (Taiwan)

This paper presents a current-driven JK reconfigurable hybrid boost converter that achieves a wide voltage conversion ratio (VCR) range of 7×–30× and delivers 11W output power at 110V / 100mA, targeting electrical stimulator applications. Compared to a conventional boost converter (CBC), the proposed design utilizes series-parallel flying-capacitor (SPFC) stages and a negative-coupled inductor to reduce the inductor current ripple by over 60% and 15% for VCRs ranges of 7×–20× and 20×–30×, respectively. Furthermore, the JK-Controller and current-driven technique dynamically adjust the converter operation based on the stimulus strength setting, leading to a significant reduction in the voltage·ampere (V·A) metric and achieving a stimulation efficiency of 87.3%.

This work proposes a low-frequency double step-down (DSD) converter integrated with a GaN-based high-frequency recycle converter. The proposed architecture ensures a sufficiently long on-time of 400 ns while achieving effective output ripple suppression, reducing ripple to 6 mV—an 11× improvement over conventional designs. Leveraging high switching frequency and enhanced inductor slew capability, the converter delivers fast transient response. For a 1-A to 5-A load step, the output exhibits a 69-mV undershoot with a 907-ns recovery time; conversely, a 5-A to 1-A step results in a 74-mV overshoot and an 848-ns recovery time, corresponding to 8.2 mV/A performance. The proposed system achieves a peak efficiency of 96.51%.

This paper proposes a Four-Phase Flying Capacitor Shared Dynamic (4PFCSD) Hybrid Converter, optimized for high current delivery and integrated with a Four-Phase Temperature Management (FPTM) system. To enhance light-load efficiency, a phase-shedding strategy enables two-phase operation in discontinuous conduction mode (DCM), achieving up to 74.2 % efficiency at a 100 mA load. The converter supports a wide voltage conversion ratio (VCR) of up to 0.5, covering the full duty cycle range from 0 % to 100 %. A hierarchical power delivery (HPD) 3D package is employed to suppress electromagnetic interference (EMI), reducing high-frequency noise by 15 dB. The FPTM system improves thermal performance, increasing per-phase efficiency by at least 7 %, and enabling a peak overall efficiency of 91.4 % at a 5 A load.

This paper presents a Monolithic Bidirectional Dual-Gate (MBD) Gallium Nitride (GaN) High Electron Mobility Transistor (HEMT) switch enhanced with Split Source Field Plates (SSFPs). The monolithic architecture reduces both device area and on-resistance (<tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\mathrm{R}_{\text{on}}$</tex>) compared to conventional discrete topologies. The inclusion of SSFPs effectively moderates electric field concentration, mitigates current collapse, and preserves low Ron under high-voltage off-state stress. Experimental results show that the proposed switch limits Ron degradation to just 42 % after repeated current collapse events. Additionally, the device area is reduced by 31% relative to back-to-back discrete GaN HEMTs. These advancements improve both efficiency and integration, positioning the proposed switch as a compelling solution for next-generation bidirectional power applications.

This paper presents a Hammir tandem mirror confinement performance analysis based on Realta Fusion’s first-of-a-kind model for axisymmetric magnetic mirror fusion performance. This model uses an integrated end plug simulation model including, heating, equilibrium and transport combined with a new formulation of the plasma operation contours (POPCONs) technique for the tandem mirror central cell. Using this model in concert with machine learning optimization techniques, it is shown that an end plug utilizing high temperature superconducting magnets and modern neutral beams enables a classical tandem mirror pilot plant producing a fusion gain Q &gt; 5. The approach here represents an important advance in tandem mirror design. The high-fidelity end plug model enables calculations of heating and transport in the highly non-Maxwellian end plug to be made more accurately. The detailed end plug modelling performed in this work has highlighted the importance of classical radial transport and neutral beam absorption efficiency on end plug viability. The central cell POPCON technique allows consideration of a wide range of parameters in the relatively simple near-Maxwellian central cell, facilitating the selection of more optimal central cell plasmas. These advances make it possible to find more conservative classical tandem mirror fusion pilot plant operating points with lower temperatures, neutral beam energies and end plug performance requirements than designs in the literature. Despite being more conservative, it is shown that these operating points have sufficient confinement performance to serve as the basis of a viable fusion pilot plant provided that they can be stabilized against magnetohydrodynamic and trapped particle modes.

The proposed bidirectional load switch (BLS) enables bidirectional current conduction while effectively blocking reverse current, providing efficient and reliable power management. It operates with a maximum input voltage (V<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">IN</sub>) of 48 V and supports load currents (I<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Load</sub>) up to 25 A, achieving a low on-resistance (R<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</sub>) of 11.2 mΩ. A driving current limiter (DCL) is implemented to regulate the gate-driving strength and suppress inrush current, allowing the bidirectional GaN (Bi-GaN) switch to turn on smoothly. This results in a rising propagation delay (T<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">pdr</sub>) of 347.4 μs and a rise time (T<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">r</sub>) of 936.7 μs, reducing inrush current by 91.4%. Additionally, the spike-reduced turn-off circuit (SRT) enables fast turn-off with a 409.7 ns falling propagation delay (T<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">pdf</sub>) and 483.6 ns fall time (T<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">f</sub>), reducing voltage overshoot by 89.5% to protect on-chip devices. The Bi-GaN device also adopts a split-source field plate (SSFP) structure, limiting the R<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</sub> increase to only 28.5% after 168 hours of stress testing, thereby ensuring long-term reliability and performance stability.

The proposed GaN-based hybrid gate driver (HGD) consists of two types of inverters and achieves a low quiescent current (IQ) of 23.2μA with a fast-operating frequency of 25MHz. At the same time, the automatic pre-charge technique (APC) senses the voltage of the bootstrapped capacitor and reduces the standby mode leakage current (ILKG) from a few milliamps to 62μA. Therefore, the efficiency is greater than 92% at the entire output load. Finally, the soft startup clamping technique (SSC) limits the peak voltage from 2.51kV to 620V, reducing power consumption during soft-start and preventing 650V GaN devices from being damaged by high-voltage stress. As a result, the LLC converter achieves a peak efficiency of 98.6% and complies with the 80 Plus Titanium and Energy Star standards for power supply units.

The UHD FO WLP design that will be required for future HPC and AI devices places stringent requirements on the lithographic patterning of the RDL and VIA. The patterning technology must be sufficiently flexible to accommodate multiple design modifications and provide rapid tape out support for the accelerated development of innovative semiconductor devices. The material must possess enhanced dielectric properties, enabling the patterning of the bottom via profiles with a profile less the 5 µm, with the film thickness remaining at 5 µm, and proving the sustainable development of materials. The combination of the patterning with the recently developed digital lithography system and high-resolution polyimide dielectric ensures that the technology, materials, and processes meet the requisite advanced packaging standards.

This paper proposes a two-phase hybrid buck-boost converter, which meets the criteria of USB PD 3.1, with an auxiliary inductor LAUX to achieve soft switching by the zero voltage switching (ZVS) technique at light loads. Besides, two interleaving phases can reduce the inductor current to half of that conventional design. Benefiting from a coupled inductor with a negative mutual inductance (M<0), the equivalent I<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$_{\mathrm {L(AC)}}$ </tex-math></inline-formula> becomes small to achieve low output voltage ripple due to large equivalent inductance Leq in a steady state. Based on the loading current, the phase shedding can change the number of driving phases for high efficiency. Moreover, a transient enhancement circuit is proposed to speed up transient response time. The proposed circuit achieves the maximum inductor current ripple reduction of 9.09% and the maximum P<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$_{\mathrm {AC\_loss}}$ </tex-math></inline-formula> reduction of 17.36% at D=0.5. Experimental results show 96.1% peak efficiency. In the case of the load step 0.5A to 5A, the recovery time and undershoot are reduced to <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$10.7\mu $ </tex-math></inline-formula>s and 133mV, respectively, and in the case of the load step 5A to 0.5A, the recovery time and overshoot are reduced to <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$9.4\mu $ </tex-math></inline-formula>s and 147mV, respectively.