Research Institute of Semiconductor Devices

The response time and sensitivity in the visible spectral range of a commercial MG-32 pyroelectric detector based on the organic crystal of tetraaminodiphenyl (NZPP Vostok JSC) with a 0.5 mm thick polypropylene input window are studied. The sensor time constant is varied by connecting a capacitance $$C$$ in the range from 2 nF to 3.8 $$\mu$$ F to the feedback circuit of the receiver amplifier. With increasing capacitance in the range of 0.1–3.8 $$\mu$$ F, the receiver time constant increased linearly from 0.2 to 5 ms, and at lower capacitances it reached saturation, setting a limit of $$\approx$$ 25 $$\mu$$ s. The voltage sensitivity is tested using a diode laser ( $$\lambda=637$$ nm); at $$C=0{.}1$$ $$\mu$$ F, it is 3600 V W $${}^{-1}$$ , which is 8 $$\%$$ less than the sensitivity of the receiver without a polypropylene window. The equivalent noise power is virtually independent of the feedback capacitance in the range of $$C=0{.}002{-}0{.}1$$ $$\mu$$ F and is $$0{.}8\times 10^{-10}$$ W Hz $${}^{-1/2}$$ , while the detectivity is $$10^{9}$$ cm W Hz $${}^{-1/2}$$ . These characteristics are approximately one or two orders of magnitude superior to those of other commercial pyroelectric detectors and the Golay optoacoustic cell, making the receiver under study quite promising and versatile for many applications.

Plasma-enhanced chemical vapor deposition (PECVD) is a critical technique in integrated circuit manufacturing. As semiconductor devices continue to scale down in advanced technology nodes, the details of PECVD processes are difficult to be captured by traditional Technology Computer Aided Design (TCAD) approaches. In this study, we present a Monte Carlo approach to predict the profile evolution of Si3N4 thin film deposition by PECVD at feature scale. By employing a new transport algorithm for reactive species in vacuum, our method achieves an atomic-level modeling of deposition profile evolution within acceptable computational time. Experimental validation demonstrates that this model achieves a mean prediction errors below 10 % for the deposition of trenches with different aspect ratios.

Silicon Carbide (SiC) possesses many superior electrical properties and is one of the most popular semi-conductor materials in the field of power electronics. SiC-based power devices feature high voltage withstand capability, low ON-resistance, and excellent thermal conductivity. Due to their bipolar conduction design, Insulated Gate Bipolar Transistors (IGBTs) achieve some of the highest power levels among discrete power devices. Therefore, SiC-based IGBT devices have significant research prospects and application potential. However, limited by the reliability of SiC devices, especially the gate oxide interface, there are currently no commercial SiC IGBT products available worldwide. In this study, the degradation of threshold voltage and conduction characteristics of 20 kV/15 A SiC IGBT devices under High Temperature Gate Bias (HTGB) stress is demonstrated and investigated for the first time. Furthermore, TCAD simulation is employed to establish the relationship between defect changes at the gate oxide interface and the degradation of threshold voltage (V<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">TH</inf>) and specific differential ON-resistance (R<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">diff,sp</inf>) in SiC IGBT devices. The results indicate that the degradation of V<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">TH</inf> and R<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">diff,sp</inf> is primarily affected by both gate voltage and temperature. The findings provide valuable insights for the design and application of SiC IGBT devices.

The paper studies Schottky diodes with Pt/n-GaAs contacts fabricated by electrochemical deposition. The results unveil the dependence of the electrophysical parameters of the diodes with a diameter of contacts from 5 to 500 <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\boldsymbol{\mu}\mathbf{m}$</tex> on the annealing temperature. The diodes are annealed in nitrogen at 300-550°C for 10 minutes. The barrier height of annealed Pt-GaAs diodes drops from 0.95 to 0.88 <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\mathbf{eV}$</tex> with decreasing diameter; the ideality factor varies from 1.04 to 1.1. Annealing at 300°C enhances the barrier height and ideality factor for smaller diodes (5–50 <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\boldsymbol{\mu}\mathbf{m})$</tex>: for the <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$5-\boldsymbol{\mu}\mathbf{m}$</tex> diode, the barrier height increases from 0.89 to 0.94 eV, while the ideality factor decreases from 1.07 to 1.03. At 400°C, the barrier height reverts to the initial value (before annealing), while the ideality factor remains close to 1. The thermal stability of Pt/n-GaAs diodes persists up to 450°C; however, the ideality factor increases. The degradation of electrophysical characteristics begins at 500°C and it can be related to the formation of defects at the interface. The obtained temperature dependencies of electrophysical characteristics are explained by interphase reactions, including the formation of <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\mathbf{PtAs}_{2}$</tex> and PtGa phases that are the key determinants of Schottky barrier properties and thermal stability of the Pt/n-GaAs system.

All modern precision analog-to-digital converters (ADCs) for voltage conversion use the integrating method as an intermediate conversion. In implementing this method, the linearity of the conversion function can be influenced by the dielectric absorption of the integrating capacitor. The task of investigating its impact on the conversion accuracy of precision integrating ADCs, which sum the results of the conversions of adjacent partial cycles, is quite relevant for ADCs of the Σ-architecture, where fundamentally there is an error due to the desynchronization caused by mismatched completion times of the partial and full conversion cycles. The objective of the research is to develop a new class of integrating ADCs with intermediate integrating voltage conversion into a pulse-width-modulated signal, which sums the results of the conversions of partial cycles (ΣT-ADCs), and to study the influence of the dielectric absorption of the integrating capacitor and the number of partial conversion cycles on accuracy through simulation modeling. A computer model has been developed in NI Multisim. Experimental research has been conducted, and the values of the standard deviation of the linearity of the ADC conversion function have been obtained, without taking into account the dielectric absorption of the integrating capacitor, as well as with the addition of the equivalent circuit of the integrating capacitor to the model with a series of absorption coefficient values - 0.01; 0.03; 0.05; 0.07; 0.1.

Views Icon Views Article contents Figures & tables Video Audio Supplementary Data Peer Review Share Icon Share Twitter Facebook Reddit LinkedIn Tools Icon Tools Reprints and Permissions Cite Icon Cite Search Site Citation Valentin Lantsov, Alexander Koryakin; Creation of a spatially distributed detection system for unmanned aerial systems. AIP Conf. Proc. 29 March 2024; 3021 (1): 060028. https://doi.org/10.1063/5.0199472 Download citation file: Ris (Zotero) Reference Manager EasyBib Bookends Mendeley Papers EndNote RefWorks BibTex toolbar search Search Dropdown Menu toolbar search search input Search input auto suggest filter your search All ContentAIP Publishing PortfolioAIP Conference Proceedings Search Advanced Search |Citation Search