Robert Bosch (China)

Electric vehicles (EVs) are becoming increasingly attractive for last-mile delivery due to their low operating costs and reduced emissions. However, widespread adoption is hindered by high upfront investments, limited public charging infrastructure, and long charging durations. To address these challenges, we explore a complementary strategy that enables EV fleets to generate revenue through vehicle-to-grid (V2G) energy transactions, while improving charging accessibility through on-the-go solar energy harvesting (SEH). In this work, we formulate a vehicle routing problem for an EV fleet equipped with V2G and SEH capabilities with the objective of reducing the overall delivery costs, while accounting for vehicle load capacities and customer time window constraints. We propose a learning-to-optimize approach (LA) that scales efficiently to problem instances involving hundreds of customer locations and multiple discharge station visits for V2G operations. Using the Solomon benchmark datasets, we compare the performance of the proposed LA with a genetic algorithm (GA). Our results show that LA achieves reasonable solution quality while being 18 times faster than GA, demonstrating its effectiveness for large-scale EV fleet route optimization.

Model-free reinforcement learning (RL) has enabled adaptable and agile quadruped locomotion; however, policies often converge to a single gait, leading to suboptimal performance. Traditionally, Model Predictive Control (MPC) has been extensively used to obtain task-specific optimal policies but lacks the ability to adapt to varying environments. To address these limitations, we propose an optimization framework for real-time gait adaptation in a continuous gait space, combining the Model Predictive Path Integral (MPPI) algorithm with a Dreamer module to produce adaptive and optimal policies for quadruped locomotion. At each time step, MPPI jointly optimizes the actions and gait variables using a learned Dreamer reward that promotes velocity tracking, energy efficiency, stability, and smooth transitions, while penalizing abrupt gait changes. A learned value function is incorporated as terminal reward, extending the formulation to an infinite-horizon planner. We evaluate our framework in simulation on the Unitree Go1, demonstrating an average reduction of up to 36.48% in energy consumption across varying target speeds, while maintaining accurate tracking and adaptive, task-appropriate gaits.

The vehicle–road–cloud continuum represents a promising frontier for cyber-physical systems, particularly in the realization of safety-critical V2X services. While containerization and orchestration frameworks such as Kubernetes offer scalable resource management, their dependability assumptions diverge significantly from the stringent safety guarantees required in the automotive domain. This paper presents a dependability-aware coordinator, inspired by automotive safety principles, designed for deployment at roadside infrastructure. We implement a prototype atop Kubernetes and deploy it across multiple urban intersections. The coordinator continuously monitors V2X warning pipelines, detects faults, and dynamically reallocates workloads to maintain service continuity. Through a connected automatic emergency braking use case based on infrastructure-side perception, we demonstrate how mainstream IT technologies can be extended and adapted to fulfill automotive-grade dependability requirements. This work bridges the methodological gap between automotive safety assurance and modern cloud-edge orchestration, advancing the safe deployment of V2X services.

AAPCS (Procedure Call Standard for Arm Architecture) A set of conventions that defines register usage, parameter passing and stack alignment during function calls, ensuring consistency across different parts of programs in ARM-based systems. ABI (Application Binary Interface)A specification that defines how program modules and components interact at the binary level, specifying data type sizes, calling conventions, register usage, system call conventions and binary object formats to ensure compatibility across different compilers and programming languages. ADC (Analog-to-Digital Converter)A device or circuit that converts an analog signal into a digital signal. AEABI (ARM Embedded Application Binary Interface)A specialized form of ABI for embedded software on Arm platforms. AHB (Advanced High-performance Bus)A high-speed bus defined within AMBA, used for communication between the CPU, memory and high-speed peripherals in a microcontroller. ALU (Arithmetic Logic Unit)A digital circuit within a processor that performs arithmetic and logical operations. AM0 (Abstract Microcontroller with Cortex-M0 processor)An abstract microcontroller defined for the purpose of learning microcontroller organization; named AM0 for ease of reference. AMBA (Advanced Microcontroller Bus Architecture)A set of protocols for communication between the functional blocks (CPU, memory, peripherals etc.) in Arm-based system-on-chip (SoC) designs. APB (Advanced Peripheral Bus)A low-power, low-bandwidth bus defined within AMBA, used for interfacing peripherals in a microcontroller. ASCII (American Standard Code for Information Interchange)A character encoding standard for electronic communication, representing text in computers and other devices. CISC (Complex Instruction Set Computer)A CPU design philosophy that uses a large set of instructions, each capable of executing complex tasks, aiming to reduce the number of instructions per program.

About this ChapterThis chapter includes a minimal startup code and a linker script file (also called a scatter file) used for the assembly programming exercises in this book. What do we learn? What are the software components of an OS-less system? What is the structure of the startup code?What initializations does it perform?Towards the end, we will take a look at a simple linker script file to get a basic understanding of how to place various program sections into the processor memory.To understand the startup code, let us first understand various software components that make up a program. C.1 OS-LESS SYSTEMThe system we have discussed in this book is standalone, without any operating system (OS), commonly known as a bare-metal system.Figure C.1 shows the structure of a typical OS-less system.

1. Cortex-M0 Devices Generic User Guide (DUI 0497A)The User Guide (UG) provides the list of Cortex-M0 features with a brief explanation on each.UG includes the complete instruction set, which would be useful in chapters 4-11 while writing programs in assembly language.UG also explains the exception model and details of the system peripherals SysTick and NVIC, which would help you go deeper into exception and interrupt handling, covered in chapters 10, 11 and 18.For most parts of this book, UG should provide a reasonably good first-level reference.2. Cortex-M0 Technical Reference Manual (Revision: r0p0)The Technical Reference Manual (TRM) is a brief (70 pages!) yet comprehensive document that provides a summary of all the blocks of Cortex-M0.After providing a summary, TRM points to the respective section in the Armv6-M Architecture Reference Manual for more details.3. Armv6-M Architecture Reference Manual (DDI 041C)Armv6-M Architecture Reference Manual (Armv6-M ARM), is the 'mother' document for all the processors based on Armv6-M architecture, including Cortex-M0.It contains complete details about the architecture: registers, instruction set, memory model, exception model and details of system peripherals SysTick and NVIC.Armv6-M ARM contains two sections: Application-Level Architecture and System-Level Architecture.The "Application-Level Architecture" section describes registers, instruction set and memory model.There is a section on "Alphabetical list of ARMv6-M Thumb instructions", which would be specifically useful in case you need to know every detail of an instruction.The section on "System-Level Architecture" describes exception handling, SysTick and NVIC. Keil MDK Complete User's Guide SelectionThis document is available through Books Window inside Vision Integrated Development Environment (IDE).It contains Vision User's Guide, which describes the IDE in detail, including the user interface, project creation and build process, debugging interface and debugger features, and additional features like peripheral simulation, utilities and command-line reference.

This chapter discusses how arrays, structures and pointers are implemented. An array is a block of memory containing elements of the same type. The base address of the array is the same as the address of the first element, referred using the name of the array itself. While the arrays are used to store the elements of the same type, structures are used to store elements of different types within a single data structure. A pointer is a data element that holds a memory address. C provides the same syntax for arrays and pointers to access the content. Implementation of a pointer to a structure is similar to the implementation of a pointer to an array. The effect of reading or writing a pointer with an unknown address could be completely unpredictable. Hence, a pointer containing a junk value could be difficult to debug and often gets to be a nightmare for programmers.

This chapter explains the various types of statements that make up an assembly program. It focuses on how an assembly program organized into sections and how to write a function made up of program instructions. The chapter explores the different types of data sections and defines various types of data elements. An assembly program is composed of several types of statements, each serving a specific purpose. The four main types of statements include comments, labels, instructions and directives. An assembly language file is organized as sections. The section names are defined in a standard called executable and linkable format. The text section consists of instructions to be executed by the processor. These instructions are written in the assembly language as defined by the processor's instruction set architecture. A data section contains the data elements used by the instructions for various computing operations.

Fractional derivatives generalise integer-order derivatives, making them relevant for studying their convergence in descent-based optimisation algorithms. However, existing convergence analysis of fractional gradient descent is limited in both methods