SK Group (South Korea)

ABSTRACT This paper presents a 12‐bit, high speed charge‐sharing analog‐to‐digital converter (ADC), targeting low area and low power in wide bandwidth integrated RF transceivers for ultrasound diagnostic medical devices. The ADC comprises charge sharing digital‐to‐analog converter (DAC) with unit array capacitors with low threshold voltage devices for small area and low on resistance respectively. The circuit uses sample and hold circuit based on bootstrapping to reduce the effect of third harmonic. The dynamic latch comparator with adaptive power control improves the power efficiency. Furthermore, the asynchronous SAR logic delay cells are digitally controlled to minimize the power consumed by the digital part. The ADC achieves an effective number of bits (ENOB) of 11.40 bits and signal to noise distortion ratio (SNDR) of 70.39 dB at the input frequency of 500 kHz. The designed ADC is implemented with a 0.13 μm CMOS process occupying an area of 1600 μm × 505 μm. The designed SAR ADC draws 0.8 mA current per channel at a sampling rate of 30 MSPS when operated at a 1.5 V power supply.

As the demand for high-speed memory interfaces continues to grow, the need for effective testing methodologies becomes increasingly critical. Traditional automatic test equipment (ATE) systems are limited in their capability to test advanced signaling methods such as pulse amplitude modulation-4 (PAM-4) due to their reliance on non-return-to-zero (NRZ) signaling. This article presents a PAM-4 transceiver designed to bridge the gap between the tester and the memory, boosting the PAM-4 testing data rate up to 48 Gb/s using existing NRZ-based ATE. The proposed work provides enhanced transition slope and ratio level mismatch (RLM) control through precise gate voltage adjustment, resulting in improved test accuracy. The prototype was fabricated in 40-nm CMOS technology and occupies an active area of 2.34 mm<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup>. The proposed work operates at 48 Gb/s/pin, demonstrating an energy efficiency of 1.85 pJ/bit in write mode and 2.97 pJ/bit in read mode for the PAM-4 test, respectively.

High-bandwidth memory (HBM) has enabled substantial advancements in bandwidth-intensive applications, including large-scale artificial intelligence models. HBM is typically integrated with other systems-on-chip (SoCs) through a silicon interposer, and the primary bottleneck in aggressively scaling the bandwidth in next-generation HBM systems stems from significant crosstalk caused by closely spaced, high-density parallel interconnects in the interposer. While crosstalk avoidance code (CAC) has emerged as a promising solution, prior CAC schemes suffer from low bit efficiency and considerable hardware overhead. This article proposes an efficient CAC scheme, WITCH, which employs a novel weighted coding strategy. Unlike prior approaches that consider all channels identically, WITCH assigns different weights to channels based on their relative positions in the array, enabling more bit-efficient crosstalk suppression. We also present WITCH with additional shielding (WITCH-AS), an extension of WITCH that incorporates additional shielding to further reduce crosstalk levels. Our coding schemes achieve high bit efficiency, up to 17.3% higher than state-of-the-art techniques while providing an identical level of crosstalk reduction. Simulation results using an industry-proven channel model demonstrate that WITCH and WITCH-AS improve eye height by 10.1%–49.4% and 17.1%–51.1%, respectively. Furthermore, we propose an area- and energy-efficient hardware implementation that can be integrated into real-world HBM systems. The design reduces area and critical path delay by 31.0% and 28.2%, respectively, compared with conventional designs. Finally, we propose a compatible simultaneous switching output (SSO) noise mitigation technique that can be seamlessly integrated into WITCH to further enhance signal integrity under high-speed, high-density operating conditions.

Low-level light therapy (LLLT) and light-emitting diode (LED) therapy have gained popularity in aesthetic dermatology for their effectiveness and convenience in treating skin aging through photobiomodulation (PBM). Recent advancements have led to the development of a new near-infrared (nNIR) LED device with a broader spectrum, aiming to enhance skin rejuvenation and hair growth. This study aims to clinically evaluate the efficacy of this nNIR device. The study included two segments: skin rejuvenation and hair growth evaluation. For skin rejuvenation, 20 participants aged 45-59 used an nNIR LED facial mask for 30 minutes, five times a week over 12 weeks. Parameters such as wrinkle count, skin moisture, elasticity, and density were measured. For hair growth, 25 participants aged 20-55 applied the same device to the scalp daily for 20 weeks, assessing hair growth at 6, 13, and 20 weeks. Skin rejuvenation showed significant improvements, with wrinkles decreasing by up to 27.22% and skin texture, elasticity, moisture, and density also improving. Hair growth evaluation indicated a 1.33% increase in hair count by 20 weeks, with high participant satisfaction and no adverse reactions reported. The nNIR LED device demonstrated clinical efficacy in skin rejuvenation and hair growth, highlighting the benefits of a broader spectral range in PBM. While further research with larger and more diverse populations is recommended, this nNIR LED device suggests significant potential for advancements in aesthetic treatments. This journal requires that authors assign a level of evidence to each article. For a full description of these Evidence-Based Medicine ratings, please refer to the Table of Contents or the online Instructions to Authors www.springer.com/00266 .

CO Oxidation Pt nanoparticles undergo reactant-driven disintegration during CO oxidation, producing mobile Pt-CO species that migrate to CeOx-TiO2 interfaces. Electronic coupling with Ce stabilizes Pt single atoms and clusters, while oxygen replenishes vacancies, enabling continuous Pt-CO diffusion. This interface-driven dynamic restructuring greatly increases the accessible Pt sites and enhances low-temperature CO oxidation performance. More in article number 2506990, Chunjoong Kim, Young-Sang Yu, Hyun You Kim, and co-workers.

This article introduces an adhesive interposer-based reconfigurable multi-sensor patch interface with on-chip quantized time-domain feature extraction, tailored for heterogeneous physiological and environmental monitoring. A proposed patch concept includes integrated micro-scale structures for comfortable pressure-based reconfiguration, allowing easy attachment and detachment of various sensor elements. For embedding edge-computing capability into a miniaturized patch device with a conventional legacy microcontroller, its multi-sensor interface integrated circuit (IC) is proposed to include on-chip analog feature extraction and classification engines of quantized time-domain convolutional neural network (QTD-CNN) and one-shot computing binary neural network (BNN). The design employs 1-bit past-data quantization, analog normalization, and flexible time window schemes to minimize leakage problems in conventional analog engines and supports reconfigurable operations for healthcare and environmental applications. This interface IC includes five types of readout frontends for chemo-resistive sensors, electrochemical sensors, biopotentials, bioimpedance, and photoplethysmogram, where every path is designed to provide both wide dynamic range (DR) and compensation capability of gain and offset. A system-level prototype of the adhesive interposer-based reconfigurable patch interface has been developed, demonstrating its effectiveness in gas event and arrhythmia detection with hit rates of 91% and 92%, respectively.