STEAG (Germany)

Für ein Heizkraftwerk von Steag New Energies wurde ein Wärmespeicher konzipiert und wird derzeit gebaut, um die Dampfversorgung effizienter zu sichern. Zurzeit wird parallel zu einer mit einem Abhitzekessel (AHK) kombinierten Gasturbine ein Dampferzeuger betrieben, welcher für Störungsfälle auf Minimallast gehalten wird. 
\nDurch den Speicher entfällt der Minimallastbetrieb, da dieser die Versorgung bei Störung übernimmt, bis ein Dampferzeuger hochgefahren ist.
\nDie Auslegung ist wie ein Rohrbündelwärmeübertrager, nur mit Speichermaterial, welches Energie bei der Entladung durch ein Phasenwechsel von flüssig zu fest abgibt, auf der Mantelseite und Wasser/dampf auf der Rohrinnenseite. Die Rohre haben axialen Wärmeleitstrukturen, erarbeitet in Kooperation zwischen F. W. Brökelmann und DLR, um die geforderte Leistung bereitzustellen.

Increasing the flexibility of conventional power plants is one key challenge for the massive integration of highly volatile renewable energy resources into the German and European power system. Flexible power plants ensure the security of supply by compensating fluctuations in the electrical grid caused by intermittent renewable energy production from wind and sun.

With gas becoming a fuel of choice for clean energy, Liquefied Natural Gas (LNG) is being transported and re-gasification terminals are being set up at several locations. Re-gasification of LNG leads to availability of considerable cold-energy which can be utilized to gain power and efficiency in a Gas Turbine (GT) based Power Plant. With a number of LNG Re-gasification Terminals coming up in India & around the globe, setting up of a high efficiency CCPP adjacent to the terminal considering utilization of the cold energy to augment its performance, and also save energy towards re-gasification of LNG, provides a feasible business opportunity. Thermodynamic analysis and major applications of the LNG re-gasification cold energy in Gas Turbine based power generation cycle, are discussed in this paper. The feasibility of cooling GT inlet air by virtue of the cold energy of Liquefied LNG to increase power output of a Combined Cycle Power Plant (CCPP) for different ambient conditions is analyzed and also the effect on efficiency is discussed. The use of cold energy in condenser cooling water circulating system to improve efficiency of the CCPP is also analyzed. Air cooling capacity and power augmentation for a combined cycle power plant based on the advanced class industrial heavy duty gas turbine are demonstrated as a function of the ambient temperature and humidity. The economic feasibility of utilizing the cold energy is also deliberated.

Several haze studies were conducted in a test environment where UV lamps and test chambers were used to simulate a wafer fab environment. This study was designed to investigate reticles experiencing different cleaning processes in a real wafer production environment. A split test was carried out to benchmark two different fabs: an 8" R & D fab and an 8" memory production fab. Reticles cleaned with UV treatment and hot DI water were exposed on ArF scanners for up to 80 hours over a period of two months. Starlight inspection before and after laser exposure confirmed no significant defect count increase after exposure. Ion chromatography (IC) results from masks cleaned on a new Steag MaskTrack cleaner suggest that hydrogenated water (H₂-H₂O) and ozonated water (O₃-H₂O) processes can further reduce the sulfate and ammonium ion residual count by 40%. UV + hot water cleaning also shows advantages in phase and transmission preservation where less than a 0.2 degree phase angle loss per clean can be achieved.

Today, the industry is suffering from the consequences of residue and contaminants on the mask surface as they significantly affect the printing quality of the reticle. Thus a good control of the mask cleanliness via its optical properties is becoming essential to minimize this impact. The AUV5500 is specifically addressing organic contaminants. The principle of the tool set-up, its process functionality is presented. Preliminary data on the impact of organic contaminants on binary and embedded phase shift masks optical properties and the tool cleaning capability are analyzed and discussed.

Progress towards 65 nm next-generation lithography requires unprecedented global CD uniformity, with the actual ITRS 2002 roadmap proposing 4.2 nm 3/spl sigma/ (dense lines) for 65 nm binary masks. Since resolution requirements are satisfied only by using chemically amplified resists (CARs), exposure and post-exposure bake (PEB) are key processes to successful mask making, both introducing global CD errors. Develop and etch processes potentially contribute further global CD errors. The global CD uniformity can be improved significantly by adaptive PEB, especially for CARs showing moderate to strong PEB sensitivity, like NEB22. With the 25-zone hotplate of the APB5500 bake system, facilitated through a novel calibration mask with 25 equidistant temperature sensors within the resist plane, an appropriate temperature profile can be applied during PEB. This temperature profile is automatically calculated by an adaptive optimization algorithm, based on 2-dimensional spline fitting of a CD measurement. A CD-uniformity improvement (dense lines) from 4.8 nm 3/spl sigma/ to 3.9 nm 3/spl sigma/ (/spl cong/20%) on a state-of-the-art production mask is achieved for the chrome layer (ASI, after strip inspection).

Negative-tone chemically amplified resists (nCARs), like NEB22 are promising candidates for next-generation lithography, e.g. 90 nm and 65 nm technology node and next-generation lithography. For these resists, e-beam exposure and post-exposure bake (PEB) are most critical processes, since these resists show a strong sensitivity to post-exposure delay (PED) in vacuum during e-beam writing of about 0.5 nm/h, and in air while waiting for PEB. Further, such resists show a strong PEB temperature sensitivity of up to 8 nm/K. The multi-zone hotplate approach of the APB AFB 5500 bake system with its use prior temperature uniformity results in excellent global CD-uniformity already. However, all kinds of systematic large area effects of processes, e.g. blank coat/bake, exposure, PED, the PEB itself, etch loading, etc. may transfer in additional systematic CD-errors. Such systematic, repeatable errors can be reduced during PEB by superimposing an appropriate non-uniform temperature profile onto the regular, optimized uniform bake temperature profile, thereby compensating for such CD-non-uniformities. The required temperature profile can automatically be calculated from a suitable gobal CD measurement, determined in a typical process flow. The compensation of CD-errors resulting from vacuum PED and hotplate temperature characteristics is demonstrated here, by using automated temperature profile calculation. The global CD uniformity was improved significantly, the achieved results show a typical reduction of about 20-30%, from a total global range of about 9nm to about 6-7nm on leading-edge production photomasks.

According to the recently released 1999 National Technology Roadmap for Semiconductors, the SID extension junction will be in the range of a few tens of nanometers for the up coming 180 nm and 130 nm nodes. Although the junctions have to become shallower, a decreasing sheet resistance is required. The formation of ultra-shallow junctions is mainly influenced by three important parameters, these are: dose and energy control during ion implantation, a controlled gaseous ambient during RTA (rapid thermal anneal), and a controlled and reproducible thermal budget during RTA. The requirements for production tools have become progressively more stringent, but the crystal off-orientation of the wafer surface condition as an issue in reproducible USJ formation has been neglected. In Si wafer production, the exact [100] orientation of the wafer surface is determined by the ingot sawing accuracy and typically done with a tolerance of +0.1/spl deg/. Prior to this experiment, however, the influence of such a variance in the wafer off-orientations on the junction characteristics had not been investigated. For our experiments repeatable "off-axis" from [100] sliced 200 mm silicon wafers were implanted with /sup 11/B/sup +/, /sup 75/As/sup +/ or /sup 31/P/sup +/ at a tilt and twist angle of 0/spl deg/ to investigate the effects on junction depth and sheet resistance. The acceleration voltage varied between 500 eV (/sup 11/B/sup +/) and 5 keV (/sup 75/As/sup +/). The off-orientation varied between exact 0/spl deg/ and the channeling-reduction-angle for boron of 7.00 (e.g. 0.35/spl deg/, 1.0/spl deg/, 4.0/spl deg/). Species depending data of as-implanted distributions as well as soak time (1050/spl deg/C 10 s) and flash annealed (with a ramp rate of 350 Ws) wafers are presented and the influences of the off-oriented sliced wafers on junction depth and sheet resistance are discussed.

Opus ™, which stands for “Optimized Uniformity Simulator”, has been described in the literature as a powerful tool to assist in the optimization of temperature uniformity in the STEAG Electronic Systems series of rapid thermal processors. Historically, this tool has been used extensively for a variety of silicon processing. With this simulation, the temperature uniformity of 100 mm Si3N4 encapsulated GaAs with a dual silicon implant anneal at 847°C, 40 s was optimized to <2°C across the wafer. Ramp rates ≤20°C/s were obtained without slip.