STMicroelectronics (Malta)

The objective of this study is to compare the results from experiment and modeling on simplified models with those from analytical solution. The target is to understand if simple analytical models or tools can be used for fast indication and preliminary evaluation of material behavior. Simple samples and respective models will be built and evaluated for warpage at temperatures of interest, namely room temperature and reflow temperature. Following this an analytical approach using Timoshenko beam formula will be evaluated and results compared with the experimental and modeling results. Finally, it will be decided if and how a simplified tool can be developed for fast and preliminary results for material comparison basis as a means of eliminating material that will not reach the desired performance prior to building more elaborate models or samples. The analysis focuses on bi-material structures for the time being and hence is more suited as a rough estimate for frame based packages, though an example for a Ball Grid Array (BGA) package is also presented. The assumptions and limitations of this methodology will be outlined. Keywords—packaging, thermo-mechanical modeling, Timoshenko equation, warpage, finite element analysis (FEA), package design, analytics (key words)

One of the main challenges of semiconductor packaging is package size reduction. The challenges that this drive introduces are experienced across all stages of product evolution. Starting from chip design, where the same architecture or added functionality needs to be fitted in an even smaller area this challenge is carried over to assembly processes where the need for higher precision and tighter tolerances will be experienced. The end result will be that a device with similar or improved functionality will be occupy less space. This paper will present some methodologies developed and deployed at finite element modeling stage in order to support virtual characterization of reduced package size at early development stages. The target of these methodologies is to provide guidelines for package designers, characterization engineers and modeling engineers at an early stage of product development, in order to support and address the challenges related to package miniaturization. Typical challenges at early characterization include the inability to perform accurate measurements such as device deformation. Due to the significantly reduced footprint, measurement equipment traditionally used to measure deformation of semiconductor device may encounter challenges. The deformation of the single device may be so low, that errors within the equipment or measurement limit will be of the same order of the deformation itself. While this may indicate the deformation of the device to be on the trivial scale, the reality is that some devices in particular sensing devices require accuracy at the nanometer scale.