Silicon Designs (United States)

In this paper we show feasibility of miniature, high-g MEMS capacitive accelerometers with full-scale ranges of 400 to 10,000g and that are capable of measuring high-g navigation events.

Growth of polycrystalline silicon from fluidized bed reactors (FBR) produces two general types of silicon products: granular material (diameters on the order of mm) and homogeneously nucleated material often called nanopowder (diameters in the range 10–100 nm). Nanopowder particles tend to be amorphous and have a spherical morphology with an average particle diameter of ~80 nm. Granular material is generally spherical, highly twinned, polycrystalline with crystallite sizes that can reach 200 nm, and includes regions of porosity. The porosity is ~1–4 volume percent, and only the smallest pores exhibit evidence of amorphous regions along the pore surface. The amount of nanopowder that agglomerates on the granular material has been identified using transmission electron microscopy, but agglomeration plays only a minor role in the overall growth process. Therefore, it is proposed that the primary mechanism for granular formation in commercial FBR is chemical vapor deposition, and the pores are associated with nanopowder agglomeration and incomplete sintering.

This article reports on the performance of audio, video, multimedia, and other high-data-rate in-home networking applications. The article starts by describing the problems encountered in power line communication channels in terms of frequency response and noise characteristics, and explains how in-home power line LANs can be extended to the neighborhood transformer. OFDM physical layers providing speeds of 45 Mb/s and 200 Mb/s as well as QoS and security are introduced. Finally, the results of large tests involving several thousands of nodes are described.

The author describes a capacitive accelerometer technology using sense element structures fabricated on the surface of a substrate or wafer. The sense element consists of an asymmetrically shaped flat plate of metal supported above a substrate surface by two torsion bars mounted on a central pedestal. The sense element is free to rotate around the torsion bars. Capacitor plates located on the substrate surface are used to detect the rotation. Fabrication of sense elements is done by selective electroforming in which a metal is electroplated onto a conductive substrate through a patterned photoresist layer. To produce suspended sense elements, the sense elements are fabricated partially on the top of a sacrificial spacer material deposited earlier. After the sense elements have been formed, the spacer material is then selectively etched, leaving the sense element supported only where it was formed directly on the substrate surface. >

A new mixed mode simulator is described, which combines a behavioral timing simulator, a switch level simulator, and a new circuit-level simulator based upon the ADEPT timing simulation algorithm. These simulation algorithms are combined into a single, consistent, interactive MOS simulator. In addition, STAFAN fault simulation is provided at the transistor level to grade vectors to be used in the testing phase of design. In this paper, each algorithm is described as well as the interfacing required between each of the simulation methods. Several examples are presented to demonstrate the utility of the L-Simulator. Circuit simulation is performed on a wide range of CMOS counter sizes, from 2 to 32 bits, showing tremendous reductions in CPU time as compared to SPICE, without loss in accuracy. A novel multi-mode simulation facility is also introduced, further decreasing the CPU time requirements for simulation. A second example shows how the performance and area of a CMOS latch is optimized using circuit modification techniques during simulation. Finally, a 73,200 transistor design of an 8051-like CPU is simulated in behavioral, switch level, and finally in circuit/mixed modes.