Silicon Technologies (United States)

The data bottleneck has emerged as a fundamental challenge in learning based image restoration methods. Researchers have attempted to generate synthesized training data using paired or unpaired samples to address this challenge. This study proposes SeNM-VAE, a semi-supervised noise modeling method that leverages both paired and unpaired datasets to generate realistic degraded data. Our approach is based on modeling the conditional distribution of degraded and clean images with a specially designed graphical model. Under the variational inference framework, we develop an objective function for handling both paired and unpaired data. We employ our method to generate paired training samples for real-world image denoising and super-resolution tasks. Our approach excels in the quality of synthetic degraded images compared to other unpaired and paired noise modeling methods. Furthermore, our approach demonstrates remarkable performance in downstream image restoration tasks, even with limited paired data. With more paired data, our method achieves the best performance on the SIDD dataset.

Versatile Place and Route (VPR) enabled the exploration of diverse FPGA architectures. OpenFPGA extended VPR through bitstream generation and added silicon compilation. Our work is one of several efforts to use this combination to build commercial devices, which, to achieve competitiveness, has necessitated several improvements to routing and elsewhere for area, power, and performance. Fitting to the MCNC and VTR benchmarks using this work, our first improved routing pattern yields a 22% reduction in metal loading, a 14% reduction in routing multiplexer input pin count per function tile, and a 10% reduction in source to farthest sink paths. For this, routed length increased 5%, the proportion of net detours increased 11%, router heap operations increased 16%, and router iterations increased 42%, as the unmodified VPR router worked harder on routing with fewer switches but without introducing any routing failures. This work provides the first steps to a routing compiler for OpenFPGA/VPR, much as ASIC/SoC flows use a memory compiler.

Test vehicles are important circuits for process yield learning at early stage. In-house customized standard cell libraries should also be evaluated from the yield perspective. In this paper, we propose novel logic test vehicles to offer high resolution diagnosis capability of in-house designed standard cell libraries. Both stuck-at and cell-aware faults are injected to evaluate the diagnosability of the test vehicles. Nearly ideal cell-level diagnosis results can be obtained to reflect the FEOL/MEOL yield detractors of the process technology under development. All standard cells in libraries are embedded in the test vehicles with even distributions. The designed test vehicles are compatible with commercial automatic physical design flow and have statistically significant area when limited volume of chips are considered.

Most existing RGB-based trackers target low frame rate benchmarks of around 30 frames per second. This setting restricts the tracker's functionality in the real world, especially for fast motion. Event-based cameras as bioinspired sensors provide considerable potential for high frame rate tracking due to their high temporal resolution. However, event-based cameras cannot offer fine-grained texture information like conventional cameras. This unique complementarity motivates us to combine conventional frames and events for high frame rate object tracking under various challenging conditions. In this paper, we propose an end-toend network consisting of multi-modality alignment and fusion modules to effectively combine meaningful information from both modalities at different measurement rates. The alignment module is responsible for cross-style and crossframe-rate alignment between frame and event modalities under the guidance of the moving cues furnished by events. While the fusion module is accountable for emphasizing valuable features and suppressing noise information by the mutual complement between the two modalities. Extensive experiments show that the proposed approach outperforms state-of-the-art trackers by a significant margin in high frame rate tracking. With the FE240hz dataset, our approach achieves high frame rate tracking up to 240Hz.

As the interconnect density of chiplets increases rapidly, some physics related defects appeared, such as coupling defects, etc. These defects are hard to detect with ordinary pseudo-random sequence patterns, some special test patterns are needed. Besides, the chip warpage caused by the thinning of 3D chips manufacturing and the uneven stress around TSVs or micro bumps will bring clustered faults of interconnections. For these defects, the repair rate of conventional interconnect redundancy method will be decreased. This paper proposes a physical-aware interconnect testing and repairing method of chiplets, using specific test patterns and clustered faults redundancy circuits to improve the interconnect test coverage and repair rate of chiplets. We also propose automatic repair circuits and the repair data synchronization scheme between multiple dies, so that the calculating and programming of repair data do not need to rely on the ATE programming, and the synchronization of the repair data between multiple dies can be done by hardware circuits automatically, which ensure the interconnection correctly after repairing.

This paper presents the design of a high-resolution time-to-digital converter (TDC) which uses a fully symmetric sense-amplifier-based flip-flop (SAFF) with improved delay chains. Simulation results show that the proposed flip-flop has a small metastability window compared with the other SAFFs. Additionally, the delay and the power are smaller. A high-speed Vernier TDC is also proposed with time resolution of 2. 5ps based on the novel SAFF.

Floorplanning, as an early step in physical design, will greatly affect the PPA of the later stages. To achieve better performance while main-taining relatively the same chip size, the utilization of the generated floorplan needs to be high and constraints related to design rules, routability, power should be honored. In this paper, we propose a two-step framework, called TOFU, for floorplan whitespace reduction with fixed-outline and soft/pre- placed/hard modules modeled. Whitespace is first reduced by iteratively refining the locations of modules. Then the modules near whitespace will be changed into rectilinear shapes to further improve the utilization. To ensure the legality and quality of the intermediate floorplan during the refinement process, a constraint graph-based legalizer with a novel constraint graph construction method is proposed. Experimental results show that the whitespace of the initial floorplans generated by Corblivar [1] can be reduced by about 70% on average and up to 90% in several cases. Moreover, the resulting wirelength is also 3% shorter due to a higher utilization.

For the 3 nm technology node, horizontal gate-all-around nanosheet devices offer a non-disruptive process transition from fin technologies with the advantage of full 3D design flexibility and better short-channel control. For SRAM cell design, this enables non-digital n/pFET balancing. In this paper, a performance and variability-aware DTCO flow is used to benchmark nanosheet SRAM cells against fin technologies at 3 nm node, targeted at 45 nm CPP and 21 nm MP. The impact of gate length, fin height, number of nanosheets, effective n/pFET widths, channel doping, and vertical nanosheet pitch is studied. Despite the lower parasitic capacitances of fins, the design freedoms of nanosheets enable superior SRAM operation in terms of both $V_{\min}$ and read delay even at smaller cell areas.

Optical flow, which captures motion information across frames, is exploited in recent video inpainting methods through propagating pixels along its trajectories. However, the hand-crafted flow-based processes in these methods are applied separately to form the whole inpainting pipeline. Thus, these methods are less efficient and rely heavily on the intermediate results from earlier stages. In this paper, we propose an End-to-End framework for Flow-Guided Video Inpainting (E <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> FGVI) through elaborately designed three trainable modules, namely, flow completion, feature propagation, and content hallucination modules. The three modules correspond with the three stages of previous flow-based methods but can be Jointly optimized, leading to a more efficient and effective inpainting process. Experimental results demonstrate that the proposed method outperforms state-of-the-art methods both qualitatively and quantitatively and shows promising efficiency. The code is available at https://github.com/MCG-NKU/E2FGVI.