Siliconware Precision Industries (Taiwan)

The material extractions of split cylinder resonator (SCR) and Fabry-Perot open resonator (FPOR) are for the unprocessed material, and the coplanar waveguide grounded (CPWG) is proposed for the substrate processed. The CPWG is implemented on 2-layer structure with 50 um thickness film. We compare the phase and insertion loss between measurement and simulation of lines to extract Dk and Df. There are no differences for the extractions of unprocessed material. For the extraction of processed material, Dk is smaller 0.1 and Df is larger 0.003 than unprocessed extraction up to E-band frequency. The material is changed slightly after the substrate processes.

The number of I/O on substrate is closely related to via land layout. Each I/O requires corresponding via, so as the I/O count increases, the density of via lands also increases. If the via size is maintained while increasing via land density, it is necessary to enhance via-to-via land registration capability. In this paper, we focus on the key factors affecting substrate via to via land registration accuracy. The tested parameters include the diameter of laser via arranged in a circular pattern, the number of laser vias, and the exposure division, the result shows that the laser via diameter and the exposure division are primary factors influencing registration accuracy, while the number of laser via has no significant effect. To achieve the optimal registration value, 4 X um laser via size should be used in combination with block exposure registration.

This paper is to demonstrate the solutions to improve package warpage through material selection and processing techniques. The simulation executes predicting the chip module warpage and stress performance regarding the large body size of package in comparison of three different chip module sizes and point out the challenges and mitigation plan.

With the development of artificial intelligence (AI) and high-performance computing (HPC) technology, advanced packages such as CoWoS (Chip on Wafer on Substrate) have become more popular in recent years due to its outstanding signal transmission speed and space management efficiency. Nevertheless, such high-power applications and the large size of heterogeneous integrated package may lead to thermal and high package warpage problems. In that case, the high stiffness heat spreader is usually used to solve the problem of large warpage. However, structural damage caused by stress and additional thermal resistance from the interface between heat spreader and die top surface have occurred. In terms of stress and thermal issues, optimizing packaging material selection and high thermal conductivity thermal interface material (TIM) are widely used to reduce the stress risk and enhance thermal performance. Therefore, it is important to accurately predict mechanical stress performance and thermal behavior. In this study, the thermal conductivity that considers real application of TIM needs to be extracted to ensure the FO-EB-T (Fan-Out Embedded Bridge with TSV) package thermal performance. In order to achieve this purpose, junction-to-case thermal resistance (ӨJC) measurement of large lidded FCBGA thermal test vehicle (TTV) is firstly measured to ensure the silicon based/graphite/alloy based TIMs thermal performance with liquid-cooling test fixture. Scanning acoustic tomography (SAT) and destructive physical analysis (DPA) are measured to check the TIM coverage and bond line thickness (BLT). Then, thermal conductivity which considers the interface effect is calculated by heat transfer equation using ӨJC, TIM coverage and BLT results. After extracting the thermal conductivity from the TTV measurement, a thermal simulation is constructed to ensure thermal behavior of the large lidded FO-EB-T test vehicle with the liquid cooling system using FloTHERM. Finally, the mechanical performance of the FO-EB-T is simulated by ANSYS to check the warpage and stress behavior. The structural material optimization is proposed to ensure the package warpage performance while reducing the chip module epoxy molding compounds (EMC) stress risk. Overall, the paper proposes a method that can extract the thermal conductivity of TIMs in real application. And further ensure not only the thermal performance but also mechanical behavior of large lidded FO-EB-T by thermal and mechanical simulation. Above that, the FO-EB-T package development that can save the design of experiments (DOE) and the thermal behavior consider real application are being proposed.

In the past, optimizing the signal integrity (SI) of high-speed SerDes signals in the packaging substrate required drawing the substrate layout first. The drawing files are then imported into the simulation software to create a 3D model and perform 3D EM simulation. Finally, confirm whether the S parameter generated by the simulation meet the specifications. If the specifications are not met, the drawing will be modified and the above steps will be repeated until the S parameter meet the specifications. This article discusses the use of Python syntax to write a 14-variable automated 3D modeling program, and writes a script to automatically import it into simulation software for simulation and generation of S parameters. The use of parametric 3D modeling programs eliminates the need to draw substrate layouts during initial SI evaluations, and model building only takes 1 second, significantly reducing the time spent on the above-mentioned previous methods. In addition, the generated 3D model occupies less than 1% of the hard disk space of previous models, the DRAM usage for model operation is 65% of that of previous models, and the total simulation calculation time is 20% of that of previous models. In the actual case of SerDes with a data rate of 112Gbps PAM4, the differential insertion loss simulation result at 28GHz using the model generated by the program is -2.3dB, while the differential insertion loss at 28GHz using the actual substrate layout is -2.4dB, with a difference of less than 0.5dB. In addition, the differential return loss simulation result at 28GHz using the model generated by the program is -16.4dB, while the differential return loss simulation result at 28 GHz using the actual substrate layout is -15.2dB, with a difference of less than 3dB. The proposed method has demonstrated its effectiveness and good accuracy and can be used to improve the efficiency of SerDes SI analysis.

In this study, an indium sheet was applied to a flip-chip ball grid array product and subjected to a ball mount reflow process (maximum temperature: 245°C) to observe sintering of the indium sheet. Regarding void formation caused by residual flux, different flux amounts were applied to determine whether reducing the flux quantity mitigates void formation.

This study mainly explored the application of indium sheets in the manufacturing of flip chip ball grid array (FCBGA) products. Because such products must undergo a high-temperature ball mount reflow process, the residual flux evaporates under high temperature reflow process and generates multiple voids on the indium surface. Due to the above limitations, the selection of flux is very important for the application of metal TIM for flip chip package products.