Socionext (Japan)

Abstract A new user function was developed to simulate carbon macrosegregation in medium to large-sized steel ingots, derived for use in the post-processing stage of casting simulations. This new proposed formulation accounts for critical parameters such as cooling rate, thermal gradient, and ingot geometry, and can be implemented within commercial simulation software to estimate steel carbon content. The methodology was first applied to an industrial-scale 36-tonne ingot, comparing simulation and experimental analyses. Characterisation of the industrial ingot, performed by sectioning and chemical analysis, showed good agreement between the carbon segregative index values predicted by the user function and those experimentally measured. To further assess the reliability of the model, a second case study was conducted on a 40-tonne ingot using the same approach. The results confirmed the predictive capability of the developed function, which can be effectively employed to evaluate carbon macrosegregation in medium to large-sized ingots, particularly for medium- to low-alloy steel grades. Graphical Abstract

Le présent article analyse le rôle central d’une image intrigante dans la poétique de Moderato cantabile : celle de la mort feinte. Il montre d’abord qu’elle se trouve au cœur de la tension que le roman institue entre scènes (initiale et finale, notamment), dialogue et récit, mais aussi entre urgence et passivité. Puis, en venant à réinscrire l’œuvre dans le contexte des expérimentations romanesques des années 1950 et 1960, il examine ce qui fait de la mort feinte l’image d’une dynamique contradictoire par laquelle l’absence de moyens se renverse et devient un moyen poétique, un moyen de prendre l’innommable en charge.

In this article, we demonstrated a high-throughput gate-level-pipelined 8-bit multiply-accumulate (MAC) unit with a long feedback loop using low-voltage rapid single-flux quantum (LV-RSFQ) logic. The long feedback loop in the MAC unit is an obstacle for high-throughput operation because the logic gates must wait for the delayed inputs from the feedback loop. The LV-RSFQ logic makes high-frequency operation even more difficult by larger and more variable feedback delay. We design the feedback loop by using counter-flow clocking and adding many D flip-flops to divide the long feedback loop into shorter paths. The target clock frequency of the MAC unit with a feedback loop was set to 30 GHz by the experimental results of the MAC unit without a feedback loop. We model the clock frequency and its circuit overhead in a feedback loop to design the feedback loop in the MAC unit achieving 30 GHz with a minimum overhead. The test chips are fabricated using the national institute of advanced industrial science and technology (AIST) 10-kA/cm <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$\boldsymbol{^{2}}$</tex-math></inline-formula> Advanced Process 2. We have successfully obtained high-throughput 30-GHz operations in the LV-RSFQ MAC unit with a long feedback loop by using the model-based design. The maximum operating frequency of the MAC unit reaches 40 GHz.

An ADC with a sampling rate of tens of GS/s and a high input bandwidth can greatly ease the design of wireless network systems. Such ADCs help in simplifying the analog front end design by relaxing the requirements for anti-alias and anti-image filtering. Having a bandwidth of up to 7.2GHz facilitates direct sampling on the 5G full FR1 band including LTE-U and WiFi 6/7 networks. However, the available state-of-the-art high-speed ADCs operating at 20GS/s or higher are designed mostly for wireline communications [5] and are not suitable for wireless base station applications where a high spectral dynamic range with an NSD of -147dBFS/Hz and an SFDR of 70dB are required to support 1024-QAM and higher modulations. The other high-resolution ADCs available in the range from 5-20GS/s [1–4] have higher power consumption, larger area and insufficient SFDR to be reliably used in the previously mentioned applications. The reported ADC achieves 24GS/s sampling rate with an input bandwidth of 7.2GHz as well as 76dB SFDR and -147.5dBFS/Hz NSD with high power efficiency and small area.

This work proposes a design methodology that saves the power dissipation under voltage over-scaling (VOS) operation. The key idea of the proposed design methodology is to combine critical path isolation (CPI) and bit-width scaling (BWS) under the constraint of computational quality, e.g., Peak Signal-to-Noise Ratio (PSNR) in the image processing domain. Conventional CPI inherently cannot reduce the delay of intrinsic critical paths (CPs), which may significantly restrict the power saving effect. On the other hand, the proposed methodology tries to reduce both intrinsic and non-intrinsic CPs. Therefore, our design dramatically reduces the supply voltage and power dissipation while satisfying the quality constraint. Moreover, for reducing co-design exploration space, the proposed methodology utilizes the exclusiveness of the paths targeted by CPI and BWS, where CPI aims at reducing the minimum supply voltage of non-intrinsic CP, and BWS focuses on intrinsic CPs in arithmetic units. From this key exclusiveness, the proposed design splits the simultaneous optimization problem into three sub-problems; (1) the determination of bit-width reduction, (2) the timing optimization for non-intrinsic CPs, and (3) investigating the minimum supply voltage of the BWS and CPI-applied circuit under quality constraint, for reducing power dissipation. Thanks to the problem splitting, the proposed methodology can efficiently find quality-constrained minimum-power design. Evaluation results show that CPI and BWS are highly compatible, and they significantly enhance the efficacy of VOS. In a case study of a GPGPU processor, the proposed design saves the power dissipation by 42.7% with an image processing workload and by 51.2% with a neural network inference workload.

A fully synthesizable injection-locked phase-locked loop (IL-PLL) for digital clocking is proposed in this letter. The phase-locked loop (PLL) is implemented in a 5-nm CMOS process, with only digital standard cells are used. With proposed triple-path operation and digital offset control for digital-to-time converter (DTC), low-jitter fractional-N frequency synthesis, and highly-linear spread-spectrum clocking are realized with low-power consumption. The PLL core area is 0.0036 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . With 100-MHz reference frequency, better than -234.7 dB figure-of-merit (FOM) is achieved in the fractional-N mode, with -44.3 dBc worst-case fractional spur. The proposed PLL has the smallest chip area, highest FOM, and lowest fractional spur among ring oscillator (RO)-based fractional-N PLLs in sub-20-nm processes.

An innovative X-ray inspection technology, named XSpectra ® , has been developed with the aim to improve the current state of art in the field of real-time detection of contaminants in food products on production lines. The technology architecture is based on modules equipped with a 128 pixels CdTe array detector each read-out by full-custom FrontEnd ASICs. A full-custom Multi-Channel-Analyzer reconstructs the radiation spectrum, which is then processed by advanced Neural Network algorithms performing both image reconstruction and foreign bodies detection. The experimental characterization of XSpectra ® has demonstrated the sensitivity of the fully operating system to photon energies down to about 10 keV at events rates up to several millions of photons per second. A line-width of 8.5 keV FWHM has been measured, at room temperature, on the 60 keV photo-peak of a synchrotron radiation in low-rate conditions. A spectral non-linearity error within ±0.5% has been obtained within the energy range 25 keV - 100 keV. The effective capability of XSpectra ® to detect currently undetectable low-density contaminants inside real food products has also been proved.

[Background and Motivation] System in Package (SiP) is pulling the evolution of technology instead of deep submicron of LSI. SiP assists coming AI/IoT/5G world. SiP has many implementation variations. When we examine the chip and package implementation technique for the target product, it's important task to find the optimal solution for the product considering trade-off between cost and performance. Compared with mass production products, it's important to optimize costs especially for small volume production products. Moreover, in terms of performance, compared to conventional packages, for high frequency products and SiP, since the margin becomes small and confirming system level electrical characteristics are necessary, in addition to conventional conceptual design and detail design, prototyping design is required to test its electrical characteristics while keeping lower cost. [Technical callenge] To do prototyping design at the early stage of product and find the optimum solution of the product, we created short turn-around time(TAT) iteration environment and distributed prototyping design. Quick Prototyping, which is a short TAT iteration environment, is based on the LSI/Package/PCB integrated co-design environment, estimates the chip size from the signal number of product, performs LSI design prototyping, using package automatic net assignment and the substrate auto routing, proceeds package prototype design and then confirms electrical characteristics. In the above, itfs possible to consider multiple implementation variations. In the distribution of prototype design, we utilize the LPB format (IEC 63055/IEEE 2401), have eliminated the interface(I/F) barriers between companies and tools, and have developed an environment for design prototypes and checking their characteristics throughout the industry. [Results and Conclusions] In collaboration with Semiconductor vendor Socionext Inc., as the above benchmark, 3D Flip Chip-Chip Scale Package(FCCSP) (with memory package with Package on Package(PoP) method) and 3D Fan-Out Wafer Level Package(FOWLP) (similarly in PoP method) as samples, the prototype design was created out. By comparison of the electrical characteristics, the Self Inductance of the FOWLP becomes half or less than FCCSP, the power supply noise could be suppressed. The shielding effect of FOWLP reduced the influence of crosstalk. We confirmed that FOWLP has advantage of electrical characteristics. On the cost side, in the LSI implementation of the FOWLP side, only the function blocks requiring performance were replaced with the fine node by chip partitioning, we examined to suppress the increase in cost while maintaining the performance advantage of FOWLP. With Quick Prototyping, cost and performance balance can be examined in the product review early stages, also by utilizing the LPB format for Quick Prototyping, from the negotiation stage with business partners, we can share the design data, focus on tuning the product itself and improve the competitive SiP products.

This paper describes an improved method of the variance estimation of Gaussian distribution for Histogram Matching based on Gaussian Distribution (HMGD). In our previous paper, focusing on the symmetry of the Gaussian function, we presented another method for the variance (or Gaussian width) estimation of Gaussian distribution in the original histogram. However, since the real shape of mountain like Gaussian function in the original image’s histogram does not always show the good symmetry, the variance estimation method that we previously presented did not work so well as we expected. In this paper, we newly propose the improved estimation method using regression analysis, based on curvature computation for the cumulative histogram of original image’s one. In the newly proposed method, first, we detect the histogram peak of original image’s histogram by using curvature computation; next, we perform the regression analysis for the cumulative histogram, using an approximated function of the curvature that includes the variance parameter. Also in this paper, we show some experimental results by the estimation method.