Universal Instruments (United States)

The high thermal conductivity and mechanical compliance of reflowed indium-based alloys known as solder thermal interface material (sTIM)s have made them an intriguing choice for applications with high power (heat generation) density. The physical integrity and long-term reliability of sTIM joints have yet to be analyzed to ensure the theoretical performance is achieved. Studying cross-sections from the reflowed parts allows for extensive evaluation of joint quality, voiding extent, and the state of IMCs at both sTIM/lid and sTIM/die interfaces that are helpful in reliability analysis of the parts. Due to the softness of the sTIM alloys, mechanical abrasion techniques lead to particle embedment and subsequent damage to the solder region. An alternative sectioning technique based on application of microtome sectioning tool is proposed here that can be used to generate sharp damage-free sections for metallographic analysis. In addition, peel-off test explained in this work provides important information on joint quality and the state of solder wetting at both interfaces.

Solder alloys play a significant role in estimating the reliability solder joint. An intermetallic compound (IMC) layer between the solder and the substrate occurs during the soldering process, establishing a metallurgical connection. However, the growth of this IMC can drastically deteriorate the physical and mechanical characteristics of the solder joints. Reflowing electronic assemblies several times, as is frequent in real-world applications, can increase the IMC thickness, compromising the integrity of the solder joint. This study investigates the influence of reflow number on both IMC layer growth and shear strength of solder joints. Individual solder joints of SAC305 and SAC-3.3Bi were assembled on printed circuit boards (PCBs) with an organic solderability preservative (OSP) surface finish and reflowed up to six times. The microstructure and thickness of the IMC layer were examined using scanning electron microscopy (SEM). Shear strength at various shear rates was measured using a Nordson DAGE test system. The failure mode and failure surface morphology were identified using optical microscopy. The results revealed that the IMC thickness increased with the number of reflows for both solder alloys. The shear strength dropped slightly as the number of reflows increased, and all sample surfaces exhibited ductile fractures, indicating that the shear strength of these joints is insensitive to the IMC thickness and morphology. The shear strength and IMC thickness were mathematically fitted with the number of reflows.

Abstract Soldered micro-electronics assemblies may have to survive a variety of mechanical loads in repeated drops, cyclic bending, or vibration. A very large body of work has addressed the isothermal fatigue performance of SnAgCu solder joints. This work offers a general assessment of the achievable performance of so-called hybrid solder joints formed by soldering with eutectic SnBi or SnBiAg to SnAgCu bumps on area array components. This allows for soldering at much lower temperatures than with SnAgCu alone, but the deformation and damage properties of the resulting structures depend strongly on details of the design and process. A peak reflow temperature of 175 °C was shown to be sufficient to ensure that the life of the joints remains limited by fatigue of the unmixed SnAgCu near the component. However, a higher effective stiffness of the mixed region near the substrate means that the life will be lower by 45%.

ABSTRACT Semiconductor and Semi equipment industries expect to see a strong upturn in the next few years, with advanced packaging technologies a significant beneficiary of the markets strength. 5G, AI, Edge Computing, Persistent Memory, Integrated Power Management, and the transition to sub 5nm silicon technology are all driving the need for innovative packaging solutions. These solutions integrate silicon produced with disparate process nodes and deliver maximum performance at optimal cost. Heterogeneous Integration, utilizing a multitude of interconnect methodologies (from Fan-out to Silicon Interposer, to Chiplet), addresses this challenge but requires unique solutions for efficient, cost effective die placement. High speed, high precision multi-die placement, directly and efficiently extracted from a range of different sized wafers, is critical to enable cost effective assembly. This paper looks at the challenges and potential approaches for efficient and cost effective solutions.

ABSTRACT This paper presents assembly challenges and reliability evaluation of 3D TMV™ (Three-Dimensional Through- Mold Via) and SiP (System in Package) in fine pitch ball grid arrays (FPGA). First, it presents the test matrix for various 3D TMV™ packaging assembly configurations and reliability characterizations performed under thermal cycling condition (–55°C to 125°C). The SiP test vehicles were configured with centrally located flip-chip (FC) die surrounded by eight chip scale packages (CSPs). The FC and CSPs, either with tin-lead or SAC305 balls, were assembled onto top of the FPGA interposer for subsequent assembly into a hybrid integrated configuration. Mix hybrid assemblies were characterized by X-ray for solder-joint quality and by Shadow Moiré method for warpage characterization. The assemblies were then subjected to thermal cycling between -40C and 125C for evaluation of reliability and followed for characterization of failure mechanisms. The paper presents details of design, characterization by X-ray and Moiré as well as behavior of the SiP and 3D TMV™ assemblies under two different thermal cycling conditions.

PurposeSolder paste printing is the most common method for attaching surface mount devices to printed circuit boards (PCB), and it has been reported that a majority of all assembly defects occur during the stencil printing process. It is also recognized that the solder paste printing process is wholly responsible for the solder joint formation of leadless package technologies such as land grid array (LGA) and quad-flat no-lead (QFN) components and therefore is a determining factor in the long-term reliability of said devices. The aim of this experiment is to determine the acceptable lower limit for solder paste volume deposit tolerances during stencil printing process to ensure both good assembly yield and reliability expectations.Design/methodology/approachStencils with modified aperture dimensions at particular locations for LGA and QFN package footprints were designed to vary the solder paste volume deposited during the stencil printing process. Solder paste volumes were measured using solder paste inspection system. Low volume solder paste deposits were generated using the modified stencil designs to evaluate assemble yield. Accelerated thermal cycling (ATC) was used to determine the reliability of the solder joints. Failure analysis was used to determine if the failure was attributed to the low paste volume locations.FindingsSolder joints formed with nominal paste volume survived longer in ATC compared to intentionally low volume joints. Transfer efficiency numbers for both good assembly yield and good reliability are reported for LGA and QFN devices. A lower volume limit is reported for leadless devices that should not significantly affect yield and reliability in thermal cycling.Originality/valueVery little literature is available on solder paste volume tolerance limits in terms of assembly yield and reliability. Manufacturers often use ±50 or ±30 per cent of stencil aperture volume with no evidence of its effectiveness in determining yield and reliability of the solder joints.

ABSTRACT New solder alloys (SAC with microalloying elements such as Ni, Mn and Ti, Sb or Bi) are under evaluation as potential replacements for SAC305 lead free solder. Researchers seek a lead free solder alloy with greater resistance to drop shock that also demonstrates acceptable thermal fatigue resistance. The effects of various microalloying additions to SAC alloys on the evolution of solder joint microstructure and on failure mechanisms must be understood in order to optimize the implementation of these new materials. Thus various commercial solders alloys with microalloying elements, such as SN100C, SACM and Innolot, were examined and compared to observations for SAC105, SAC 305 and eutectic SnPb alloys. Both mechanical and thermal cycling tests were performed on solder joints assembled on Cu-OSP or ENIG. The thermal history of each individual solder joint was carefully controlled and monitored by differential scanning calorimeter. Thus the effects of varying reflow parameters on the mechanical behavior in shear and shear fatigue test were analyzed. ATC reliability test was conducted on BGA components using a −40/125°C profile. Careful microstructural analysis was performed on as reflowed and failed samples. Polarized light microscopy and electron backscatter diffraction techniques were used to assess the effect of Sn grain morphology on life time of solder joints, particularly on early and late failures. The effect of variation in solder volume, composition, Sn grain morphology and PCB surface finish on solder joint microstructure and lifetime was carefully evaluated.

ABSTRACT The Semiconductor Industry has been relying for decades on Moore’s Law as the path to increase functionally and transistor count while lowering the cost/node. As we are pushing the limits we are facing a reality where going to smaller geometries is no longer offering the benefits of cost reduction, and the applications that can benefit from < 20nm process is limited to specific applications that can command high ASPs. We are at an inflection point where Advanced Packaging can play a more significant role to support further integration and cost reduction, leveraging existing Assembly technology and Foundry resources augmented by innovative initiatives from leading OSAT, Foundry and IDM’s. Traditionally, assembly equipment followed the technology developed for the foundries, especially when it comes to WLP where most of the equipment was developed to support the Wafer form factor. Breaking this wafer form factor requires development of new tools that can support reconstruction of wafers taking the KGD and “converting” them into a larger carrier that can be then processed in parallel through the entire assembly process. The lowest common denominator dictates the limit for the entire assembly line, thus the drive is to enable the largest possible panel that can be supported in all steps of the assembly process. In this Paper, Universal instruments will present a revolutionary solution enabling the highest accuracy for the largest work area without compromising UPH offering the best cost/performance and economies of scale that are essential for deployment in HVM.

ABSTRACT Component warpage is the root cause for many manufacturing defects encountered by Contract Manufactures (CMs) who develop processes for the assembly of advanced products. Current JEDEC JESD22-B112A [1] and JEITA ED-7306 [2] standards for package warpage at elevated temperature describe the measurement techniques and provide maximum warpage recommendation for FBGA and FLGA devices. Historically only the JEITA standard defines the maximum allowable elevated temperature warpage conditions for FBGAs and FLGAs. The limitation of these standards is that defining the component warpage as an absolute is not acceptable for many of the instances where Head in Pillow (HiP) failures are observed in production. For example, there are many devices that easily comply with the standards, as characterized utilizing the prescribed techniques, yet still produce HiP failures. This is observed even in situations where contamination is an unlikely cause. The intent of this paper is to describe the limitations in measurement and complexity of warpage related defects. Several case studies are used to highlight the limitations of current industry standards and to serve as a launching point for research topics into warpage induced defects.