Van Putten-Gas Energy Observatory (Netherlands)

The increasing integration of distributed renewable energy sources and electrification of energy demand require enhanced coordination between transmission and distribution system operators to optimize voltage control, congestion management, and balancing. This paper presents theLink-Chain Design Framework, a modular approach to TSO-DSO coordination that balances decentralization and performance. Four coordination options—centralized, partly decentralized, fully decentralized, and the Link-Chain Design Framework—are evaluated based on efficiency, practicability, privacy, and scalability. While decentralization adds complexity and fragments the optimization problem, it improves performance across other dimensions. The Link-Chain Design Framework uniquely supports scalable, incremental implementation, enabling gradual integration of lower voltage levels and advanced functionalities while minimizing data exchange and distributing computational effort. This framework provides a flexible, structured approach for tailoring coordination strategies to local grid conditions and implementation timelines.

Single junction crystalline silicon (c-Si) solar cells are reaching their practical efficiency limit while perovskite/c-Si tandem solar cells have achieved efficiencies above the theoretical limit of single junction c-Si solar cells. Next to low-thermal budget silicon heterojunction architecture, high-thermal budget carrier-selective passivating contacts (CSPCs) based on polycrystalline-SiO (poly-SiO ) also constitute a promising architecture for high efficiency perovskite/c-Si tandem solar cells. In this work, we present the development of c-Si bottom cells based on high-temperature poly-SiO CSPCs and demonstrate novel high-efficiency four-terminal (4T) and two-terminal (2T) perovskite/c-Si tandem solar cells. First, we tuned the ultra-thin, thermally grown SiO . Then we optimized the passivation properties of p-type and n-type doped poly-SiO CSPCs. Here, we have optimized the p-type doped poly-SiO CSPC on textured interfaces via a two-step annealing process. Finally, we integrated such bottom solar cells in both 4T and 2T tandems, achieving 28.1% and 23.2% conversion efficiency, respectively.

Abstract The non‐uniform presence of shunting defects is a significant cause of poor reproducibility across large‐area solar cells, or from batch‐to‐batch for small area cells, but the most commonly used value for shunt parameterisation (the shunt resistance) fails to identify the cause for shunting. Here, the use of equivalent circuit models to describe dark current–voltage characteristics of ZnO:Al/i‐ZnO/CdS/CIGS/Mo devices in order to understand shunting behaviour is evaluated. Simple models, with a single shunt pathway, were tested but failed to fit experimental data, whereas a more sophisticated model developed here, which includes three shunting pathways, yielded excellent agreement throughout the temperature range of 183–323 K. The temperature dependence of fitting parameters is consistent with known physical models. Activation energies and contact barriers are determined from the model, and extracted diode factors are unique across the voltage range. A case study is presented whereby the model is used to diagnose poor reproducibility for CIGS devices (efficiency ~3–14% across a 100 cm2 plate). It's shown that lower efficiencies correlated with greater prevalence of Ohmic and non‐Ohmic shunt currents, which may form due to pinholes in absorber and buffer layers respectively, whereas the quality of the main junction was constant for all cells (diode factor ~1.5–2). Electron microscopy confirmed the presence of ZnO:Al/i‐ZnO/Mo and ZnO:Al/CIGS/Mo regions, supporting the multi‐shunt pathway scheme disclosed by modelling. While the model is tested with CIGS cells here, this general model is a powerful diagnostic tool for process development for any type of thin‐film device. Copyright © 2015 John Wiley & Sons, Ltd.

Hermetic wafer-level Cu-Sn solid-liquid interdiffusion (SLID) bonding was investigated to explore the sensitivity of selected process parameters with regard to voiding and possible reduction of strength. Little or no variation was observed in the void density as a result of modifying the plated Sn thickness, the storage time between plating and bonding, the bonding tool pressure, or the thermal budget during bonding. All shear tested samples showed excellent shear strength, with an average value within 110–164 MPa. Some statistically significant differences in shear strength were found due to the variations of the process parameters. However, the differences were too small to be critical for the application. Analysis of fracture surfaces showed that the shear strengths in the lower range corresponded to fracture between the adhesion layer (TiW) and the silicon cap, while shear strengths in the higher range corresponded to fracture in the Cu3Sn formed during the bonding. The results indicate that the investigated bonding process is robust with regard to the studied process parameters.

Equipment miniaturization offers several opportunities such as an increased surface-to-volume ratio combined with high heat transfer coefficients. However, moving towards small-diameter channels demands extra attention to fouling, reliability and stable operation of the system. The present investigation explores the possibilities of hot gas flow through the porous wall of a pipe as a means to evaporate a liquid flowing in the pipe fully. A reduction of the pressure fluctuations of about 30 to 40% is obtained with this so-called contactless boiling. Because of the injected gas, wall temperatures measured are higher. The reduction in heat transfer coefficient corresponds to an insulating gas layer at the wall with an estimated thickness of 20 ¿m.

This work deals with a precise 3-D modelling of several LED board technologies mainly focused on thermal, thermo-mechanical evaluation and life time prediction to compare their performances. Main role of each LED board is to transport heat from LED die to heat sink and keep the thermal stresses in all layers as low as possible. Thermal stress has been inspected for the widest temperature range that can affect the LED boards (-40 to +125°C). Additionally, thermal stress cycles that lead to the LED board failure due to thermal fatigue have been calculated. Simulations have been completed with ANSYS structural analysis where temperature dependent stress-strain material properties have been taken into account. The objective of the analysis is to optimize not only the thermal management by thermal simulation of LED boards, but also to find potential problems from mechanical fatigue point of view.