Vanguard International Semiconductor (Taiwan)

The formation of cone defects is a side effect of the shallow trench isolation (STI) etching process, caused by the redeposition of residue from silicon nitride, silicon dioxide, or byproducts from the etching process. This study aims to explain the mechanism responsible for these defects during STI etching. The utilization of this model can enhance the design for manufacturability by streamlining the manufacturing process, reducing susceptibility to defects and process variations, and ultimately improving the reliability and manufacturability of production.

Although the p-substrate connection of p-type ESD device does not have any impact on the device's It2 while connecting the p-substrate to the ground degrades the human-body model (HBM) robustness of the device significantly. From the experiment results, adding N-type buried layer (NBL) to p-type ESD device can have the device HBM robustness invariant to the p-substrate connection. Based on the T-CAD simulations, the effect of the p-substrate connection on the HBM robustness of p-type ESD device is revealed in this paper. As HBM raises up the potential of the whole region of p-type ESD device after the onset of zapping for a while and then the high potential region of the device decreases with decreasing HBM current if the p-substrate is grounded, resulting in the current crowding. On the contrary, the high potential region of p-type ESD device does not decrease with decreasing HBM current if the p-substrate is floating or NBL is added to the device, resulting in the uniform current distribution.

For PMIC applications and especially in the automotive filed, many rigorous testing and checking in reliability concerns are required such as a long lifetime, wide operating voltages, temperature ranges and so on. Accordingly, a detailed understanding for HCI effect of LDNMOS transistor has been becoming an important part in the optimization of device design. In this study, a 20V LDNMOS transistor device is chosen for illustrating how to predict the optimum design parameter based on TCAD simulation tool.

This paper investigates a passive voltage amplification in GHz range based on piezoelectric resonators with decent electromechanical coupling (k <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">t</inf> <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> ) and high quality factor (Q). The analytical model shows that keeping the transducer capacitance (Co) sufficiently small is the key to attaining high passive voltage gain at GHz frequencies. To verify the proposed idea, two aluminum nitride (AIN) thin-film bulk acoustic wave resonators (FBAR) at 2.3 GHz with Co of only 133 fF (Type A, FoM = k <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">t</inf> <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> Q = 120) and 355 fF (Type B, FoM = 172) were implemented. As a result, high voltage gains of 21 dB (Type A) and 19 dB (Type B) have been demonstrated with reactive loadings of 120 fF and 140 fF, respectively, while achieving good input matching (S <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">11</inf> < −15dB). To the authors' knowledge, this is the first MEMS-based resonant transformer demonstrated in S-band.

The bridged T–coil circuit (BTC) and the LC T-network are well known matching circuits. These circuits are differentiated only by the bridged capacitor (C <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">B</inf> ). The two circuits have same electrostatic-discharge (ESD) performance while their bandwidths are different. Based on the complex conjugate matching theorem, the component relation model of the BCT and the LC T-network are derived in this paper. From the derivation, the bandwidth extension mechanism of the BTC is revealed as the C <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">B</inf> can equalize the coefficient of each power of s for all impedances or admittances of BTC to make them synchronize with frequency to cancel out at any frequency.

Power Integrated Circuit (IC) needs to consume huge currents so it often includes a large size device. In order to approach IC driving capabilities, 1.5 times to the simulation size can be used. In this study, 40 % reduction in IC layout can be reached after the correct simulation tool flow is adopted.

The impact of interface charges under the gate spacer on FDSOI devices integrated in low temperature process are explored. A great number of traps (~10 13 /cm 2 ) are identified on the interface between the spacer oxide and the silicon film using Terman's method for interface states characterization. Thanks to electrical characterization and TCAD simulations, it is shown that the trapped charges induce the formation of a depleted region in the vicinities of the spacer. Moreover, a strong degradation of performances on underlap channels is observed. The spacer charges influence on reliability measurements is finally explored.

Transmission Line Pulse (TLP) is often applied for Electrostatic Discharge (ESD) devices' characteristics researches. It indicates the devices' triggering-on behaviors, holding performances and thermal run-away results. In normal cases, the thermal run-away data should correlate to ESD [1]. However, the non-correlations between TLP and ESD can be observed in the gate driving circuits [2], silicide devices [3] and poly fuses [4]. In this paper, analyses for the relations between ESD and TLP are taken into discussions for large array devices (LAD).

In this paper, the whale optimization algorithm (WOA) is applied to the inverse scattering of an imperfect conductor with corners. The WOA is a new metaheuristic optimization algorithm. It mimics the hunting behavior of humpback whales. The inspiration results from the fact that a whale recognizes the location of a prey (i.e., optimal solution) by swimming around the prey within a shrinking circle and along a spiral-shaped path simultaneously. Initially, the inverse scattering is first transformed into a nonlinear optimization problem. The transformation is based on the moment method solution for scattering integral equations. To treat a target with corners and implement the WOA inverse scattering, the cubic spline interpolation is utilized for modelling the target shape function. Numerical simulation shows that the inverse scattering by WOA not only is accurate but also converges fast.

Energy handling capability of large-array devices (LADs) is one of the most dominating concerns for the designers that affect the device design and its reliability. In this paper, the improvement of the avalanche ruggedness capability by using an optional implantation layer has been investigated the first time for the application of 5-V n-channel large-array MOSFET in a bipolar-CMOS-DMOS (BCD) process. Experimental results with extensive measurements verified that the maximum avalanche current (I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">AV</sub> ) achieved from the modified device is enhanced by more than twice. Moreover, the energy in avalanche single pulse (EAS) capability is improved by more than five times. A significant improvement is noticed in the avalanche safe-operating-area (A-SOA) as compared to the original device, and the failure analysis is discussed in detail. In addition, the impact of an optional implantation layer on the total gate charge (Qg) is also compared for a LAD with a total width of 12 000 μm.