Xilinx (Ireland)

Soft X-ray tomography (SXT) enables native-contrast three-dimensional (3D) imaging of fully hydrated, cryogenically preserved biological samples, revealing ultrastructural details without the need for staining, embedding, or sectioning. Traditionally available only at synchrotron facilities, recent advances in laser-driven plasma sources have led to the development of compact soft X-ray microscopes. Achieving a resolution of 54nm full-pitch and tomogram acquisition times of 30min to two hours, we validate the system across a range of biologically relevant contexts, including protists, yeast, and mammalian cells containing polymeric and inorganic nanoparticles. These use cases establish the robustness of the laboratory based system for studying cell architecture, organelle interactions, and nanoparticle trafficking. By showing that a compact SXT system can achieve reliable high-resolution imaging across various cell types, this study highlights a major step toward making correlative cryogenic X-ray imaging broadly accessible in laboratory settings. Future developments will aim at enhanced throughput, deeper integration with correlative imaging modalities, and extension to more complex specimen types, including tissue.

Collective operations such as scatter, gather, reduce, etc are utilized broadly to implement distributed HPC applications and are the target of extensive optimization in all MPI implementations as well as dedicated collective libraries by accelerator vendors (e.g. NCCL and RCCL by NVidia and AMD respectively). We present ACCL, an open-source FPGA-accelerated collectives library designed to serve applications running primarily in Xilinx FPGAs. Compared to previous collective communication solutions for FPGA, ACCL is flexible and extensible, easily portable, and fast. We evaluate ACCL up to 8 nodes and demonstrate that ACCL outperforms OpenMPI over 100 Gbps TCP-IP for large messages.

Non-shaping dynamic element matching (DEM) randomization schemes are widely adopted for wideband Nyquistrate digital-to-analog converters (DACs) within transmitter architectures. Here, randomization translates the mismatch-induced distortion into white noise from dc to Fs/2 range. However, the DAC performance for various bands within the Nyquist range cannot be improved using non-shaped DEMs as their inherent structure cannot be made programmable. Conversely, mismatchshaping DEMs can be made tunable to shape the DAC errors over various signal bands, which makes them suitable for wireless transmitter applications. This paper presents the design methodology for high-order mismatch-shaping DEM architectures suitable for wideband Nyquist DACs. The challenge in designing high-order DEM structures for Nyquist DACs is to make them programmable to cover various signal bands within the Nyquist range and to operate them at high-frequencies demanded by the applications. Moreover, the stability of the high-order loop-filter within the DEM and its implementation cost is of great concern. This work details techniques to design programmable, stable, and hardware efficient high-order DEM structures for wideband Nyquist DACs. The DEM structures are implemented on an UltraScale+ FPGA device for prototyping and validation. Furthermore, the DEM design operation is validated by obtaining the measurement results interfacing with a 5-bit analog DAC.

The HPCG benchmark represents a modern complement to the HPL benchmark in the performance evaluation of HPC systems, as it has been recognized as a more representative benchmark to reflect real-world applications. While typical workloads become more and more challenging, the semiconductor industry is battling with performance scaling and power efficiency on next-generation technology nodes. As a result, the industry is turning towards more customized compute architectures to help meet the latest performance requirements. In this paper, we present the details of the first FPGA-based implementation of HPCG that takes advantage of such customized compute architectures. Our results show that our high-performance multi-FPGA implementation, using 1 and 4 Xilinx Alveo U280 achieves up to 108.3 GFlops and 346.5 GFlops respectively, representing speed-ups of \(104.1\times \) and \(333.2\times \) over software running on a server with an Intel Xeon processor with no loss of accuracy. We also demonstrate that the FPGA-based solution achieves comparable performance with respect to modern GPUs and an up to \(2.7\times \) improvement in terms of power efficiency compared to an NVIDIA Tesla V100. Finally, a theoretical evaluation, based on Berkeley’s Roofline model demonstrates that our implementation is near optimally tuned on the Xilinx Alveo U280.

Custom dataflow Convolutional Neural Network (CNN) inference accelerators on FPGA are tailored to a specific CNN topology and store parameters in On-Chip Memory (OCM), resulting in high energy efficiency and low inference latency. However, in these accelerators the shapes of parameter memories are dictated by throughput constraints and do not map well to the underlying OCM, which becomes an implementation bottleneck. In this work, we propose an accelerator design methodology - Frequency Compensated Memory Packing (FCMP) - which improves the OCM utilization efficiency of dataflow accelerators with minimal reduction in throughput and no modifications to the physical structure of FPGA OCM. To validate our methodology, we apply it to several realizations of medium-sized CIFAR-10 inference accelerators and demonstrate up to 30% reduction in OCM utilization without loss of inference throughput, allowing us to port the accelerators from Xilinx Zynq 7020 to 7012S, reducing application cost. We also implement a custom dataflow FPGA inference accelerator for a quantized ResNet-50 CNN, utilizing on-chip weights, the largest topology ever implemented with this accelerator architecture. We demonstrate that by applying FCMP to the ResNet accelerator, the OCM bottleneck is alleviated which enables the accelerator to be ported from Alveo U250 to the smaller Alveo U280 board with less throughput loss compared to alternative techniques. By providing a finer-grained trade off between throughput and OCM requirements, FCMP increases the flexibility of custom dataflow CNN inference designs on FPGA.

Deep neural networks (DNNs) are state-of-the-art algorithms for multiple applications, spanning from image classification to speech recognition. While providing excellent accuracy, they often have enormous compute and memory requirements. As a result of this, quantized neural networks (QNNs) are increasingly being adopted and deployed especially on embedded devices, thanks to their high accuracy, but also since they have significantly lower compute and memory requirements compared to their floating point equivalents. QNN deployment is also being evaluated for safety-critical applications, such as automotive, avionics, medical or industrial. These systems require functional safety, guaranteeing failure-free behaviour even in the presence of hardware faults. In general fault tolerance can be achieved by adding redundancy to the system, which further exacerbates the overall computational demands and makes it difficult to meet the power and performance requirements. In order to decrease the hardware cost for achieving functional safety, it is vital to explore domain-specific solutions which can exploit the inherent features of DNNs. In this work we present a novel methodology called fault-aware training (FAT), which includes error modeling during neural network (NN) training, to make QNNs resilient to specific fault models on the device. Our experiments show that by injecting faults in the convolutional layers during training, highly accurate convolutional neural networks (CNNs) can be trained which exhibits much better error tolerance compared to the original. Furthermore, we show that redundant systems which are built from QNNs trained with FAT achieve higher worse-case accuracy at lower hardware cost. This has been validated for numerous classification tasks including CIFAR10, GTSRB, SVHN and ImageNet.

A multi-lane short-reach wireline transceiver is implemented in 16nm FinFET. Taking advantage of a low-loss channel with minimum reflections, 56Gbps NRZ differential signaling is employed, using only a continuous time linear equalizer (CTLE) in the receiver to perform equalization. The transceiver incorporates low swing signaling, a central PLL with regulated CMOS clock distribution, and an injection-locked oscillator (ILO)-based per-lane skew adjustment. At the system level, a common reference clock is used to increase link margin through jitter tracking. The transceiver achieves a BER of <1e-15 over a channel with 8dB loss at 28GHz with an efficiency of 2.25pJ/bit.

Using FPGAs to accelerate ConvNets has attracted significant attention in recent years. However, FPGA accelerator design has not leveraged the latest progress of ConvNets. As a result, the key application characteristics such as frames-per-second (FPS) are ignored in favor of simply counting GOPs, and results on accuracy, which is critical to application success, are often not even reported. In this work, we adopt an algorithm-hardware co-design approach to develop a ConvNet accelerator called Synetgy and a novel ConvNet model called DiracDeltaNet$^{\dagger}$. Both the accelerator and ConvNet are tailored to FPGA requirements. DiracDeltaNet, as the name suggests, is a ConvNet with only $1\times 1$ convolutions while spatial convolutions are replaced by more efficient shift operations. DiracDeltaNet achieves competitive accuracy on ImageNet (88.7\% top-5), but with 42$\times$ fewer parameters and 48$\times$ fewer OPs than VGG16. We further quantize DiracDeltaNet's weights to 4-bit and activations to 4-bits, with less than 1\% accuracy loss. These quantizations exploit well the nature of FPGA hardware. In short, DiracDeltaNet's small model size, low computational OP count, low precision and simplified operators allow us to co-design a highly customized computing unit for an FPGA. We implement the computing units for DiracDeltaNet on an Ultra96 SoC system through high-level synthesis. Our accelerator's final top-5 accuracy of 88.1\% on ImageNet, is higher than all the previously reported embedded FPGA accelerators. In addition, the accelerator reaches an inference speed of 66.3 FPS on the ImageNet classification task, surpassing prior works with similar accuracy by at least 11.6$\times$.

A 13bit 5GS/s time-interleaved ADC is described which uses a chopping technique to reduce the effect of interleaved flicker noise spectral artefacts and to increase the ADC immunity to input signal characteristics. Enhanced offset and time-skew calibration algorithms are developed to maximize the performance in the presence of non-ideal sampling switches. At 5GS/s, the ADC dissipates 641mW while achieving a 62dB and 57dB of SFDR and SNDR respectively while maintaining a SFDR excluding HD2 and HD3 better than 70dBc across the first Nyquist band for input amplitudes down to −20dBFS.

A 40-56 Gb/s PAM-4 receiver with ten-tap decision-feedback equalization (DFE) targeting chip-to-module and board-to-board cable interconnects is designed in 16-nm FinFET. The design implements direct feedback of the first post-cursor (h1) DFE tap to reduce the number of slicers. The h1 feedback signals are directly tapped from the master latch output of the StrongArm-based slicers. A CMOS amplifier with delayed pre-charge release is used to boost and pre-condition the h1 feedback signals before being applied to current-mode logic tap cell for optimum DFE summer settling time. The receiver achieves less than 1E-12 PRBS31 bit error rate (BER) over a channel with 10-dB loss at 14-GHz consuming 230 mW. Fully adapted by off-chip software, the receiver performance demonstrates the effectiveness of direct h1 loop and the need for higher DFE taps to achieve a required BER over channels with reflections. Receiver performance over higher loss channels up to 23 dB and/or under emulated cross-talk noise injection cases are also presented.