Zuken (United Kingdom)

[Background and Motivation] System in Package (SiP) is pulling the evolution of technology instead of deep submicron of LSI. SiP assists coming AI/IoT/5G world. SiP has many implementation variations. When we examine the chip and package implementation technique for the target product, it's important task to find the optimal solution for the product considering trade-off between cost and performance. Compared with mass production products, it's important to optimize costs especially for small volume production products. Moreover, in terms of performance, compared to conventional packages, for high frequency products and SiP, since the margin becomes small and confirming system level electrical characteristics are necessary, in addition to conventional conceptual design and detail design, prototyping design is required to test its electrical characteristics while keeping lower cost. [Technical callenge] To do prototyping design at the early stage of product and find the optimum solution of the product, we created short turn-around time(TAT) iteration environment and distributed prototyping design. Quick Prototyping, which is a short TAT iteration environment, is based on the LSI/Package/PCB integrated co-design environment, estimates the chip size from the signal number of product, performs LSI design prototyping, using package automatic net assignment and the substrate auto routing, proceeds package prototype design and then confirms electrical characteristics. In the above, itfs possible to consider multiple implementation variations. In the distribution of prototype design, we utilize the LPB format (IEC 63055/IEEE 2401), have eliminated the interface(I/F) barriers between companies and tools, and have developed an environment for design prototypes and checking their characteristics throughout the industry. [Results and Conclusions] In collaboration with Semiconductor vendor Socionext Inc., as the above benchmark, 3D Flip Chip-Chip Scale Package(FCCSP) (with memory package with Package on Package(PoP) method) and 3D Fan-Out Wafer Level Package(FOWLP) (similarly in PoP method) as samples, the prototype design was created out. By comparison of the electrical characteristics, the Self Inductance of the FOWLP becomes half or less than FCCSP, the power supply noise could be suppressed. The shielding effect of FOWLP reduced the influence of crosstalk. We confirmed that FOWLP has advantage of electrical characteristics. On the cost side, in the LSI implementation of the FOWLP side, only the function blocks requiring performance were replaced with the fine node by chip partitioning, we examined to suppress the increase in cost while maintaining the performance advantage of FOWLP. With Quick Prototyping, cost and performance balance can be examined in the product review early stages, also by utilizing the LPB format for Quick Prototyping, from the negotiation stage with business partners, we can share the design data, focus on tuning the product itself and improve the competitive SiP products.

<div class="section abstract"><div class="htmlview paragraph">The electrical and electronic system in vehicles with all its components has become more and more complex. Many different stakeholders are involved and more and more parts of the development process have been shifted to the suppliers. This outsourcing results in substantial savings on the OEM side, but brings additional challenges to manage the overall system and keep the core IP within the OEM.</div><div class="htmlview paragraph">This presentation shows an approach that was adopted recently by several OEMs. It is called the “E/E-Architecture” process and applies the principles of system engineering according ISO/IEC15288. It shows the starting point by managing the requirements and how to use functions as the source of the truth over the entire design process. During the E/E Architecture phase, it is important to concentrate on the strategic design aspects. This is to model all artifacts that have influence on systems performance, reliability, and cost, but to avoid wasting efforts on the small things that can be handled later in the supplier detail development.</div><div class="htmlview paragraph">The presentation also looks at the requirements for the tools to support such a system approach with aspects like data model, variant handling, multi-user, etc. It will show the pragmatic solution building blocks available.</div><div class="htmlview paragraph">Furthermore, it will look at how OEMs can benefit from the implementation of the E/E Architecture approach in terms of quality, cost savings, and efficiency increase.</div></div>

Digital signals on PCB have been kept on being faster and faster. Transmission line simulation is used for an effective way of verification, and built into design flow in recent years. In this article, we introduce the transmission line simulation, and explain how to make use of it on actual design and CAD/CAE system integrated with it.

We have developed a new de-coupling capacitor, which is contained a small value of dumping resister. The capacitor is effective to compress impedance increase at an anti-resonance frequency when they are connected parallel to widening their low impedance range. It has been confirmed with experimental measurement, the radiated noise is reduced by the capacitors at the anti-resonance frequencies.