영상 클러스터링에 의한 인쇄회로기판의 부품검사영역 자동추출

Printed circuit board (PCB) assembly lines consist of a number of different machines for mounting electronic components onto PCBs. While high-speed placement machines are employed to assemble standard components, so-called fine-pitch placement machines are used to mount complex electronic components with high precision and by use of specific nozzles. In this paper, we investigate a typical mass production environment where a single type of PCB is assembled in a line comprising high-speed as well as high-precision placement machines. The PCB assembly line balancing problem consists of assigning component feeders, each holding a specific electronic component type, and the corresponding placement operations to machines in the line so as to minimize the assembly cycle time. To solve this problem, a two-stage solution procedure based on genetic algorithm (GA) is proposed. In the first stage, component feeders are assigned to the placement machines with the objective of balancing the workload within the assembly line. A number of candidate solutions are then transmitted to the second stage, where specific machine optimization algorithms are applied to determine the feeder-slot assignment in the component magazine of the machines and the placement sequence of the various components. As a result, fine-tuned placement operation times are achieved which reflect the individual operation mode and the actual component setup of the placement machines. Finally, from the candidate solutions the one which minimizes the actual PCB assembly time is selected.

The traditional global template matching is time consuming, has low accuracy, and cannot be adapted to rotation and scale change. The template matching technique proposed in this study improves the time, accuracy and robustness for printed circuit boards (PCB). In order to shorten the image positioning time, the image preprocessing is implemented on PCB image and the image blocks are labeled to obtain the tagged image, and the feature vector is extracted and the marking point region image is selected. The feature vector with rotation change and scale change robustness is extracted from the tagged image after labeling in the PCB image by using artificial neural network, combined with image moments for training. The marking point region image in the PCB image is selected. The scale value of the marking point region image is estimated by parametric template vector matching. The deflection angle of marking point region image is calculated by Hough transform. The obtained scale value and deflection angle value are used for fast template matching to determine the marking point positioning. The three-dimensional (3D) parabolic curve fitting is implemented in marking point positioning and adjacent pixel position to reach the sub-pixel level accuracy. The experiment showed that the proposed template matching technique for the PCB image with or without noise or angle rotation, the average position accuracy error of each translated image is lower than 7 \(\upmu \)m, and the error standard deviation is lower than 5 \(\upmu \)m. The rotation angle error average and standard deviation of angular error of Hough transform are lower than 0.2\(^{\circ }\), more accurate than orientation code (OC) method. The scale value estimation, relative error average and error standard deviation are lower than 0.004 and 0.006 for the image with or without noise. The average complete positioning time of PCB image at resolution of \(2500\times 2500\) is only 0.55 s, which is better than the 3.97 s of traditional global template matching. The results prove that the template matching technique of this study not only has sub-pixel level high accuracy and short computing time, but also has the robustness of rotation change and scale change interference. It can implement rapid, efficient and accurate positioning.

The main issue for enhancing the productivity in Printed Circuit Board (PCB) is to reduce the cycle time for pick and place (PAP) operations; i.e., to minimize the time for the PAP operations. According to the characteristics of the PAP problems, the sequence for the placement of components can be mostly treated as the Travelling Salesman Problem (TSP). In this paper, a Genetic Algorithm (GA) with External Self-evolving Multiple Archives (ESMA) is developed for minimizing the PAP operations in PCB assembly line. ESMA focuses on the issue of improving the premature convergence time in GA by adopting efficient measures for population diversity, effective diversity control and mutation strategies to enhance the global searching ability. Three mechanisms for varietal GA such as Clustering Strategy, Switchable Mutation and Elitist Propagation have been designed based on the concept of increasing the dynamic diversity of the population. The experimental results in PCB and TSP instances show that the proposed approach is very promising and it contains the ability of local and global searching. The experimental results show ESMA can further improve the performance of GA by searching the solution space with more promising results.

Recent technological innovations, namely the development of new solder pastes with increased tack life and the introduction of bypass conveyors, facilitate the use of mixed-model lines in printed circuit board (PCB) assembly. This paper presents a simulation study comparing PCB assembly lines operating in conventional batch and in mixed-model assembly mode. For the latter case, a novel group setup strategy is developed. In the first stage, component types and placement operations for each type of PCB are assigned to the machines in the assembly line with the objective of balancing the workload. In the second stage, PCB types with similar component requirements are clustered into setup families. In addition, the feeder-slot assignment for each setup family and the sequence of placement operations for each PCB type are determined. In the final stage, a cyclical mixed-model production schedule is established. The performance of the proposed solution approach is evaluated by means of a simulation study. Two alternative material flow systems are investigated: a serial conveyor which directly links one machine to the other and a flexible one that allows to bypass downstream machines in the line.

On the selection of a printed circuit board assembly line system

In this paper, we consider a repetitive routing problem which we find on a printed circuit board assembly line. There are m different printed circuit boards to be processed. As an automated manipulator embeds electronic parts in a printed circuit board from above, n identical pins from underneath protect it against overbending. A dedicated pin configuration is designed for each printed circuit board so that pins do not obstruct its own circuit. A single grasp-and-delivery robot transfers the pins one by one to arrange them from a configuration to another one. Given an initial configuration of pins and a permutable set of m required configurations, our repetitive routing problem asks to find a configuration sequence, i.e., a processing order of m printed circuit boards, and a transfer route of the grasp-and-delivery robot so that the route length over all m transitions is minimized. We first design a polynomial time approximation algorithm with factor four to a restricted version of the repetitive routing problem with a non-permutable set of configurations, i.e., with a fixed processing order of m printed circuit boards. Applying the procedure, we then show that the repetitive routing problem with a permutable set of configurations admits a polynomial time approximation algorithm with factor six.

One of the most important factors to give an inspection automation decision is the precision of measurements taken by the inspection machine. This paper aims to provide help in the selection of an automatic optical inspection (AOI) machine for a printed circuit board (PCB) assembly line of an electronics manufacturer. Since the visual inspection of soldered surfaces on a PCB is a crucial step, AOI machines bring great speed and accuracy to the inspection process. The main goal is to find the best automatic inspection machine alternative among the three AOI machine offerings according to nine selection criteria by integrating coefficient of variation statistic with TOPSIS and VIKOR, which are well-known multicriteria decision analysis methods. For this purpose, three different brands of AOI machines have been tested for the same PCBs, with 10 different components. After calculation of TOPSIS and VIKOR rank scores, the coefficient of variation of rank scores for all components is obtained and the selection of the AOI machine is finalized.

This paper discusses the component assignment problem for Printed Circuit Board (PCB) assembly lines in a computer manufacturing company. A PCB assembly line in the company has several non-identical pick-and-place machines to insert Surface Mounted Devices (SMD). On the other side, a board may have several hundreds of SMD components. Due to the various configurations of the machines, different machines have different unit assembly time for the same kind of SMD components. The question is how to assign these SMD components to those machines in order to achieve the best performance. The problem is formulated as a linear integer programming model in this paper. Although the objective of the integer programming can be the minimum balanced delay in a line balancing problem, we found the objective of minimizing cycle time to be better.

The purpose of this paper is to study the temperature effect on the Print Circuit Board (PCB) and the solder joints in the vehicle under working condition of the engine. Thermal-stress test has been used to evaluate the reliability or fatigue life of the PCB using commercially available Finite Element Analysis software, ANSYS. The thermal deformation distribution of the PCB and stress of the solder joints can be obtained. The modal analysis was carried out under the thermal and normal condition. The frequency, mode shapes, deformation and stress were obtained. It is observed that the frequency of the overall PCB assembly was decreased under thermal condition as compared to that under normal condition. The position of maximum temperature was located around the top edge of solder joints, which was close to package. And the position of maximum deformation and stress was also located around the top edge of the solder joints, which was close to package. This paper obtains the thermal stress and thermal deformation of the PCB and solder joints in the vehicle and compare the frequency of the PCB assembly under the thermal and normal condition.

In a generic surface mount printed circuit board assembly line, the largest segment of process-related defects can be ascribed to the solder paste deposition process. The amount of solder paste that is deposited significantly affects both process yields and product reliability. In order to monitor the solder deposition process, surface mount printed circuit board assembly incorporates vision systems with 3D paste inspection capability. But the possibility of capturing both data and the resulting knowledge that represents fluctuations in production mix and volume (to ensure effective continuous real-time monitoring) becomes infeasible because (i) inspection data is not archived and (ii) the inspection tools are not combined with active statistical process control. Having an information systems solution to access and retrieve the historical data from the inspection stations and perform statistical analysis on the available data set would aid continuous monitoring/improvement of the process. This paper provides an insight into the importance of historical data and a software model ('Cyberstat Advisor') that facilitates statistical process control (SPC) and data analysis in the solder deposition process. In order to assist process improvement, data generated by the solder deposition inspection machine was converted and mapped into a relational database format. The 'Cyberstat Advisor' retrieves and utilizes the information from this database. This tool uses heuristics to search and sift through the extensive database. Based on historical data, the 'CyberStat Advisor' can (i) calculate the control limits for a site in the Printed Circuit Boards (PCBs) that had been inspected and (ii) compute the process capability of the solder paste printer with respect to a particular site. This module can also plot run charts, range charts, and bar charts for any site. These visual representations help to better understand the process, facilitating in process improvement.

A deep ensemble convolutional neural network (CNN) model to inspect printed circuit board (PCB) board dual in-line package (DIP) soldering defects with Hybrid-YOLOv2 (YOLOv2 as a foreground detector and ResNet-101 as a classifier) and Faster RCNN with ResNet-101 and Feature Pyramid Network (FPN) (FRRF) achieved a detection rate of 97.45% and a false alarm rate (FAR) of 20%–30% in the previous study [34] . However, applying the method to other production lines, environmental variations, such as lighting, orientations of the sample feeds, and mechanical deviations, led to the degradation in detection performance. This article proposes an effective self-adaption method that collects “exception data” like the samples with which the Artificial Intelligent (AI) model made mistakes from the automated optical inspection inference edge to the training server, retraining with exceptions on the server and deploying back to the edge. The proposed defect detection system has been verified with real tests that achieved a detection rate of 99.99% with an FAR 20%–30% and less than 15 s of inspection time on a resolution $7296 \times 6000$ PCB image. The proposed system has proven capable of shortening inspection and repair time for online operators, where a 33% efficiency boost from the three production lines of the collaborated factory has been reported [6] . The contribution of the proposed retraining mechanism is threefold: 1) because the retraining process directly learns from the exceptions, the model can quickly adapt to the characteristic of each production line, leading to a fast and reliable mass deployment; 2) the proposed retraining mechanism is a necessary self-service for conventional users as it incrementally improves the detection performance without professional guidance or fine-tuning; and 3) the semiautomatic exception data collection method helps to reduce the time-consuming manual labeling during the retraining process.

Electronic components (EC) detection is relevant for Printed Circuit Board (PCB) manufacturing, quality inspection, and assurance (cyber-security). Moreover, at end-of-life electronic devices, the PCBs become Waste PCBs (WPCBs), the primary source of high-value materials in electronic waste. However, the recycling process is challenging because of the WPCB’s high composition diversity. EC detection in WPCBs can reduce the uncertainty about WPCBs composition and help select a better recycling process. Nevertheless, large fully-annotated datasets for the PCB domain are available at a high cost. For WPCBs, there is only one publicly available dataset, the PCB-DSLR, and it is partially labeled. As for PCBs, the FICS-PCB dataset is available. However, it contains images of modern and clean PCBs, all in good condition, while the first has broken and dirty parts. Thus, we propose a self-training strategy for object detection algorithms without needing a fully labeled dataset. In the strategy, the YOLOv5 model is used to detect the eight types of electronic components present in FICS-PCB in PCB-DSLR, which initially has labels only for integrated circuits. The process occurs through the interaction between a teacher model, trained with the FICSPCB data, and a student model, which is trained by joining the FICS-PCB data and the teacher-generated labels for PCB-DSLR. The results show that the student model performs better in the electronic components detection task, obtaining greater precision and sensitivity when compared to the teacher model. Since we are dealing with partially labeled data, we provide a low-dimensional representation of the detections of both models using t-SNE.

In this paper, a research on fatigue life estimation methods for printed circuit board assemblies (PCBA) under vibration loading is conducted. It mainly makes a comparison on fatigue life estimation results, for a FBGA mounted on the center of printed circuit board (PCB) with simply supported on all four sides and subjected to random vibration loading, between Steinberg's model and three-band method. Because Steinberg's model is a practical empirical model based on Steinberg's testing and experience, and the reference of cycles to failure, N1, based on 3s PCB displacement is an empirically determined value and uncertain for new products, using FEA to calibrate the parameter is meaningful for rapid fatigue life estimation. A finite element analysis (FEA) by ANSYS Workbench is performed to obtain the PCBA's natural frequency and the 1-s level von Mises stress of critical solder ball of the component. Using the results of FEA, the fatigue life or damage can be calculated by Steinberg's two methods. And according to the damage equivalent principle, the Steinberg's model (empirical formula) is modified to fit new PCBA's fatigue life estimation and will be verified by test in the next work.

Given the increase in digital product waste, demand for recycling of printed circuit boards (PCBs) is increasing. Precious and minor metals are often well concentrated in integrated circuit (IC) chips, especially in PCBs; hence, IC chips are primary targets for recycling. The technology for the non-destructive detachment of IC chips from PCBs is increasing in sophistication; however, the effectiveness of IC chip detachment is currently assessed manually and visually. In the present study, an automated IC chip detachment assessment method was developed, which combines multistep binarization and template matching of X-ray transmission images of crushed PCBs. To validate the method, five types of mechanically crushed PCBs from mobile phones were examined, and the developed method successfully assessed the IC chip detachment rate, with an average error rate of only 2.2% compared to visual assessment.

A profile identification system for surface mount printed circuit board assembly