글로벌형 다중대역 디지털 위성방송용 Ku-대역 LNB 개발

A design of a 5.6 GHz frequency synthesizer with switched bias LIT VCO and low noise on‐chip LDO regulator for 5G applications

A 0.2–2.5 GHz active resistive negative feedback low noise amplifier (LNA), based on current-reuse transconductance boosting technique is designed in 0.18-µm CMOS technology. The LNA has the characteristics of high gain, low noise and reasonable power consumption. Meanwhile, the input resistance feedback technology is adopted to greatly increase the matching bandwidth of the input. Post-layout simulated results get a 3-dB bandwidth of 0.2–2.5 GHz and 19.2 dB power gain. Its input/output matching is less than −10 dB in the 0.1–4.5 GHz frequency range, and the input third-order intercept point (IIP3) is greater than −9 dBm. The LNA noise figure (NF) is 2.5–3.16 dB in the 0.2–2.5 GHz. The circuit consumes 24 mW DC power from a 3 V supply and the layout size is 980 µm × 530 µm.

This paper presents the realization of high gain low Noise Figure (NF) Low Noise Amplifier (LNA) employing the variable gain amplifier. The high gain is achieved by cascading three stages while the low NF is achieved by employing the resistive feedback in the input stage. The linearity is achieved by employing the source degeneration technique. The variable gain amplifier gets turned on/off by the input signal causing the change in the transconductance of the LNA and hence the gain of LNA varies according to the input signal strength. The results show that maximum gain for the realized LNA is 21.34 dB at 1.72 GHz for M7 ON position while during M7 OFF position, the maximum gain achieved is 26.05 dB at 1.72 GHz frequency. The S11 value is less than –9 dB for the frequency range of 1.65 GHz to 3.9 GHz, i. e., having the bandwidth of 2.25 GHz and it is matched for the 50 Ω termination at input and output port. The minimum value of the NF during low conductance is 2.88 dB while during the high conductance it is 2.82 dB.

Microwave integrated systems in silicon provide a low cost, low power and high yield solution for wideband data communication, radar, and many other applications. Phased-array systems are capable of steering the radiation beam by electronic means, emulating the behavior of a directional antenna. This dissertation is dedicated to presenting various techniques to implement microwave integrated phased-array receivers in silicon-based technologies in the context of three design examples. A 24-GHz 0.18-µm complementary metal oxide semiconductor (CMOS) front-end was demonstrated. The front-end consists of a low noise amplifier (LNA) and a mixer. The LNA utilizes a novel topology common-gate with resistive feedthrough to obtain low-noise performance. The entire front-end achieves a 7.7dB noise figure and a 27.5dB power gain. A fully integrated 8-element 24-GHz silicon germanium (SiGe) phased array receiver was implemented. The receiver uses two-step downconversion and local oscillator (LO) phase shifting with 4-bit resolution. The signal is combined at the 4.8-GHz intermediate frequency. The 16 phases of 19.2-GHz LO signal are generated with a voltage controlled oscillator (VCO) and symmetrically distributed to the phase selectors at all path. Appropriate phase sequence is applied to the phase distribution transmission lines to minimize mismatch. An integrated frequency synthesizer locks the 19.2-GHz VCO output to a 75-MHz external reference. Measured array patterns show a peak-to-null ratio of more than 20dB and a beam steering range covering all signal incident angles. An integrated 4-element 77-GHz SiGe wideband phased-array transceiver was implemented. Two-step conversion is used at both the receiver and the transmitter. A differential phase of 52 GHz is generated by the VCO and distributed to all RF paths at the transmitter and receiver. The phase shifting is performed at the LO ports of the RF mixers using continuous analog phase shifters. The quadrature signal of the second LO frequency is generated by dividing the VCO frequency by a factor of 2 using a cross-coupled injection-locked frequency divider. The signal combining is performed at IF with an active combining amplifier. The receiver achieves a 41dB gain at 80 GHz with 3 GHz of bandwidth. The 52-GHz-to-50MHz frequency divider chain obtains 7% locking range.

This paper discusses the design of the narrow band cascode source degeneration Low Noise Amplifier (LNA) operational at 5 GHz frequency. The LNA was designed with standard gpdk 180 nm technology using Cadence Virtuoso tool. In this paper, source degenerated inductor with cascode and current mirror configuration have been used. For the design of input and output matching circuits, π-match and L-match have been used respectively. Performance parameters like noise factor, S-parameters, gain, linearity etc. have been analysed for the proposed design. Various kinds of analysis like sp analysis, noise analysis, dc analysis, ac analysis and harmonic analysis have been performed for the validation of design. Analog Mixed Signal (AMS) CMOS process is utilized for the design of 5 GHz LNA. This LNA achieves source degeneration inductance feedback which is useful for low noise factor for 5GHz wireless applications.

A 12 GHz low, noise converter (LNC) suitable for use in two band reception has been developed. A wideband, very low noise amplifier (LNA) and two Switchable local oscillators in the LNC make it possible to receive two frequency bands. The developed LNC has low noise figures of less than 2.5 dB (for frequency band from 11.7 to 12.2 GHz) , a high image rejection ratio of more than 90 dB, and very low local power leakage of less than -95 dbW.

The authors describe the technology development leading to a family of high-electron-mobility transistor (HEMT) monolithic low-noise amplifiers (LNAs), and present modeled and measured performance data on LNAs covering the 2-20 GHz frequency band. These amplifiers achieve noise figures comparable to their counterpart in hybrid HEMT technology. The amplifiers are configured in a cascadable design, with simultaneous low input and output VSWR, and flat gain response. Performance results include measured and modeled data for a 2-7 GHz LNA with 2.5-dB noise figure, a 2-20-GHz distributed amplifier with 9.5-dB flat gain and 3.5-dB noise figure, and a 5-11-GHz and >3.5 balanced LNA with 10-dB gain and >

We propose and experimentally demonstrate a photonic millimeter-wave frequency divider based on a super-harmonic injection-locked optoelectronic oscillator (OEO) and an optical frequency comb. The optical frequency comb generator is incorporated into an OEO loop to create broadband comb lines with low noise. By injecting a millimeter-wave with frequency around N times of the fundamental oscillating frequency f0 of the OEO, the injection signal can be down-converted to an intermediate frequency (IF) signal close to the oscillating frequency of the OEO. The free running OEO is synchronized with the IF signal via an injection locking mechanism. Consequently, it forms an injection-locked frequency divider as the frequency ratio between the injection signal and OEO's output signal is precisely equal to N. We carry out an experiment to divide the 45 GHz signal into 7.5 GHz and the experimental results agree well with the theoretical analysis. By changing the frequency of the injection signal, division ratio from 2 to 5 is also demonstrated on one setup. Due to the broadband spectra of the optical comb and low phase noise characteristics of the OEO, it is potential to realize very large division ratio and low phase noise for multiple input frequencies mf 0 .

In addition to LNA (Low Noise Amplifier) noise figure, gain and input matching, its linearity is also an important consideration. An LNA must amplify signal without adding too much noise but also remain linear even when strong signals are received. In the narrowband LNA topology, good values of S-parameters and noise performance are achieved at the expense of linearity. In order to improve LNA linearity, trade-off between several conflicting metrics is necessary together with applying some linearization techniques. In this work, importance of the LNA linearity would be given, together with overview of the up-to-date linearization techniques. Their influence on LNA measure of linearity IP3 (the third-order intercept point) would be presented.

High-performance low dropout regulator (LDO) chips are core components that provide clean power for high-precision sensors, radio frequency (RF) circuits, low noise amplifiers and other noise-sensitive circuits. In the reported literature, the designed LDO chip has advantages in certain parameters, but it cannot meet all the requirements of a high power supply rejection ratio (PSRR), low output noise and low standby current at the same time, which makes the high-end applications of LDOs greatly limited. In this paper, an LDO chip with high PSRR, low output noise and low standby current has been designed and fabricated. By increasing the loop gain, introducing an improved feedforward path, and adopting isolated power supply, the PSRR of the LDO at different frequency bands is greatly improved. By optimizing the design of the error amplifier (EA) and adding a low-pass filter to filter out the reference noise, the output voltage noise of the LDO is reduced. Within the depletion process and an optimized reference structure, the standby power consumption of the LDO is reduced without damaging the output voltage accuracy. The chip is taped out with SMIC’s 0.18 μm/5 V/BCD process. The measured PSRR of the chip is as high as 95dB at a frequency of 1 kHz, and the high-frequency (1 MHz) PSRR is above 45 dB. The amplitude of integrated output noise is below 5.4 μVrms within the frequency range of 10 Hz to 100 KHz. When the load current is zero, the measured standby current is less than 400 nA. The test results indicate that the chip has excellent performance in terms of PSRR, output noise and standby power consumption.

This letter presents a low-noise and high-gain CMOS mixer that uses a simple dynamic current-bleeding (DCB) technique. The conventional static current-bleeding (SCB) technique has high conversion gain and low noise figure at a high intermediate frequency (IF) but also has moderately high direct-mechanism flicker noise. Meanwhile, the conventional DCB technique possesses completely opposite characteristics. The proposed DCB technique obtains not only low direct flicker noise and low noise figure at high IF, but also has high conversion gain by combining only the advantageous features of both conventional techniques. Measurement results show a conversion gain of 21.2 dB and a noise figure of 16.3 dB at 10 kHz and 5.6 dB at 10 MHz, while the mixer consumes 4.2 mW at a 1.2 V supply voltage. It was implemented in a 0.11-μm CMOS process with a chip area of 0.8 × 0.8 mm2. © 2017 Wiley Periodicals, Inc. Microwave Opt Technol Lett 59:1267–1271, 2017

A wireless transceiver typically uses a PLL at the transmitter to up-convert a baseband signal to an RF frequency and uses another PLL at the receiver to down-convert the RF signal back to the baseband. Depending on the quality of the PLL clock, which is often measured by its phase noise, the process of up-conversion and down-conversion produces unwanted signals which often interfere with signals in adjacent channels and deteriorate the SNR at the receiver. In this chapter, we first provide a brief background on the transmitter and receiver concepts, and then discuss the impact of PLL phase noise on transceiver performance. Basics of Wireless Transceivers Figure 8.1(a) shows the block diagram of a simplified wireless transmitter, in which a baseband signal is up-converted to an RF frequency in a two-step process: first to an intermediate frequency (IF), and then to an RF frequency, using a local oscillator (inside a PLL). The RF signal is then fed to a bandpass filter (BPF) followed by a power amplifier (PA) and the antenna. If the oscillator produces a pure single tone, the up-converted signal will simply contain the baseband signal translated (shifted) in frequency to f RF . If the baseband signal has a bandwidth of B, the RF signal will have a bandwidth of 2B, as shown in Figure 8.1(b). However, due to the phase noise of the oscillator, the up-converted signal will also contain frequency content outside the 2B bandwidth, which may contribute to noise in adjacent receiver channels. The BPF allows the signal and the noise content within the 2B bandwidth to pass but attenuates the phase noise and other noise content that lie outside the 2B bandwidth. The PA amplifies the power of the RF signal so as to extend its reach to the intended receivers. A simplified block diagram of a wireless receiver is shown in Figure 8.2(a). The received signal from the antenna is first filtered by an off-chip surface acoustic wave (SAW) filter, then passed to a low noise amplifier (LNA), and subsequently to a mixer that down-converts the RF signal either to an intermediate frequency (IF) or directly to DC for further filtering.

Modern wireless communication equipment, point-to-point and point-to-multipoint microwave digital radios, radar equipment, microwave sources require high stability, low power consumption, and very low phase noise frequency sources in UHF band. Existing TCXO solutions can achieve -150 dBc/Hz phase noise floor at the carrier frequency of 100 MHz. The goal of this work was to create a 500 MHz TCXO with Stratum-3 stability performance (0.28 ppm over temperature, 4.6 ppm over all conditions), which can reach -155 dBc/Hz noise floor, -120 dBc/Hz at 1 KHz offset from the carrier, while providing +7 dBm of output power. The goal was accomplished by integrating in a small SMD package high performance, low frequency, Stratum-3 digitally compensated reference TCXO, low noise off-the-shelf phase locked loop (PLL) IC, and ultra low noise 500 MHz VCXO. The key solutions for this development besides solid digitally compensated TCXO design were optimization of the PLL circuit, and design of a VCXO. The VCXO is based on a 3rd overtone 100 MHz AT-cut crystal resonator with relatively high Q, passive band-pass filter, tuned on the fifth harmonic of the 100 MHz VCXO, and a free-running L-C oscillator, which is injection locked to the above mentioned fifth harmonic of the VCXO. The resulting device performance met all the stated goals and even somewhat exceeded the phase noise expectations. The sub-harmonic suppression was better than 50 dBc

This paper presents a 60 GHz low gain imbalance low noise amplifier (LNA)-phase shifter (PS) in 65 nm CMOS for phased-array receiver. The proposed LNA-PS consists of an LNA and PS. The LNA with 1-stage current steering cascode provides 1-dB step 2-bit gain control with almost constant phase response. Thus, gain imbalance of the 4-bit PS is compensated. The LNA-PS is optimized for a phased-array receiver and the measured gain for 4-bit phase states is 16.5±2.2 dB over 57–66 GHz. The RMS gain and phase errors are < 6.3° and < 0.82 dB over 57–66 GHz, respectively. The chip consumes 13 mW from 1 V power supply. The core chip size is 0.3 mm2.

A low-power-consumption (26.93 mW) 32 GHz (Ka-band) low noise amplifier (LNA) using standard 0.18 µm CMOS technology is reported. To achieve sufficient gain, this LNA is composed of three cascaded common-source stages. The output of each stage is loaded with a bandpass (or a highpass) combination of L and C to provide parallel resonance, i.e. to maximise the gain, at the design frequency. This LNA achieved input return loss (S11) of −13.3 dB, output return loss (S22) of −13.4 dB, forward gain (S21) of 10.2 dB and reverse isolation (S12) of −19.1 dB at 32 GHz. This LNA consumed only a small DC power of 26.93 mW. The chip area is only 740×500 µm, excluding the test pads.