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  • https://doi.org/10.7840/kics.2012.37b.1.59Copy DOI Icon

표준 모드를 지원하는 5Q MPI 하드웨어 유닛 설계

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Abstract

최근 모바일 장치의 사용의 증가와 복잡한 응용 프로그램의 사용이 증가하면서 MPSoC의 사용이 증가하고 있다. 이러한 MPSoC의 성능을 향상시키기 위해 프로세서의 수가 늘어나고 있는 추세이다. 다수의 프로세서 구조에서 장점이 있는 분산 메모리 구조의 효율적인 데이터 전달하기 위해서 표준 MPI를 이용한다. 표준 MPI는 소프트웨어로 제공되지만, 하드웨어로 구현하면 보다 높은 성능을 얻을 수 있다. 하드웨어로 구현된 MPI의 메시지 전송 방식으로 기존의 동기 방식(Synchronous Mode), 준비 방식(Ready Mode), 버퍼 방식(Buffered Mode)과 이 방식들을 혼합한 형태인 표준 방식(Standard Mode)가 있다. 본 논문에는 기존의 MPI 하드웨어 유닛에서 사용되던 구조에 작은 크기의 데이터를 선별하여 버퍼 방식으로 전송함으로써 전송율을 극대화 하였다. 기존의 구조에서 사용된 3개의 큐(Queue)는 그대로 같은 기능을 하고, 본 논문에서 추가된 2개의 큐(작은 준비 큐와 작은 요청 큐)을 추가하여 임계점보다 작은 크기의 데이터에 대한 처리와 저장을 담당하도록 하여 성능을 향상하였다. 제안된 구조에서 임계점을 32byte로 제한하였을 때 임계점 이하의 데이터에서 20%의 성능 개선 효과를 볼 수 있었다. The use of MPSoC has been increasing because of a rise of use of mobile devices and complex applications. For improving the performance of MPSoC, number of processor has been increasing. Standard MPI is used for efficiently sending data in distributed memory architecture that has advantage in multi processor. Standard In this paper, we propose a scalable distributed memory system with a low cost hardware message passing interface(MPI). The proposed architecture improves transfer rate with buffered send for small size packet. Three queues, Ready Queue, Request Queue, and Reservation Queue, work as previous architecture, and two queues, Small Ready Queue and Small Request Queue, are added to send small size packet. When the critical point is set 8 bytes, the proposed architecture takes more than 2 times the performance improvement in the data that below the critical point.

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