0.33 NA EUV systems for high-volume manufacturing

The impact of time‐based manufacturing practices on mass customization and value to customer

ASML NXE:3400 scanners are now commonly used for High Volume Manufacturing (HVM) of 7nm and 5nm logic devices as well as D1z memory devices. This year, ASML has introduced the NXE:3600D scanner to the market, targeting 3nm logic and D1a and D1b nodes. In this paper we will share the latest performance of these systems, including excellent overlay, critical dimension (CD) control, stability, reliability, and high productivity. Furthermore, we will address the ASML roadmap for meeting the requirements for the 2 nm node and beyond.

ASML NXE:3400 and NXE:3600D scanners are now commonly used for High Volume Manufacturing (HVM) of 7nm to 3nm logic devices as well as 10nm class memory devices. In this paper we will share the latest performance of these systems, including excellent overlay, critical dimension (CD) control, stability, reliability, and high productivity. Furthermore, we will address the ASML roadmap for meeting the requirements for the 2 nm node and beyond.

A Micro LED (μLEDs) display, a heterogeneous system, is one that integrates inorganic μLEDs and IGZO thin film transistors made on different substrates with different process flows. Millions of μLEDs are transferred from source wafers and integrated on TFT backplanes to make a display. To guarantee zero defect density, a fault tolerant design (e.g. redundancy) may be adopted. Here, we estimate the required redundancy level for a given display resolution and yields for the μLED source wafers and the transfer process of μLEDs to the backplane. This is done using a novel yield statistical model. The results may be used to assess the capital requirements and the risk involved in making such heterogeneous systems in high volume manufacturing.

While optical patterned wafer inspection systems have been successfully used for many years to both improve and control yield during wafer fabrication, their sensitivity is no longer adequate to meet advanced device manufacturing requirements. An alternative is to use wafer inspection systems based on electron-beam technology, which have been commercially available for many years. However, the relatively low throughput of these single-beam systems has kept them from being used to support high-volume manufacturing. One possible way to improve the throughput would be to use multiple columns. However, it has proven difficult in the past to build columns small enough to fit many on a 300 mm wafer and also have the performance of a large single column. Recently, a commercially available scanning electron microscope that utilizes a miniature field-emission column was shown to have adequate resolution to locate defects in a test pattern provided by SEMATECH. The column is all electrostatic and the lenses and deflectors are made of silicon using micro-electro-mechanical systems techniques. This technology can be used to build very small columns optimized for the high speed and high current requirements of electron-beam inspection.

We focus on the economical aspect of a high-volume flexible manufacturing system (HV-FMS) for agile manufacturing. We develop a model to estimate the economical behavior of HV-FMS and flexible transfer line. Under several demand patterns which have been generated from historical data, both models are simulated to evaluate the effectiveness of HV-FMS from an economical view point.

ASML NXE:3400 and NXE:3600D scanners are now commonly used for High Volume Manufacturing (HVM) of 7 nm to 3 nm logic devices as well as 10 nm class memory devices. In this paper we will share the latest performance of these systems, including excellent overlay, critical dimension (CD) control, stability, reliability, and high productivity Furthermore, we will describe the latest technology supporting the ASML roadmap for further improving cost of technology via increased productivity and share system qualification and performance data of the next HVM scanner, the NXE:3800E. Lastly the ASML NXE sustainability roadmap showing progress and steps towards a significant reduction in energy consumption per wafer exposure on NXE systems will be presented.

With the introduction of the NXE:3400B scanner, ASML has brought EUV to High-Volume Manufacturing (HVM). The high EUV power of >200W being realized with this system satisfies the throughput requirements of HVM, but also requires reconsideration of the imaging aspects of spectral purity, both from the details of the EUV emission spectrum and from the DUV emission. This paper will present simulation and experimental results for the spectral purity of high-power EUV systems, and the imaging impact of this, both for the case of with and without a pellicle. Also, possible controls for spectral purity will be discussed, and a novel method will be described to measure imaging impact of varying CE and DUV. It will be shown that CE optimization towards higher source power leads to reduction in relative DUV content, that the small deltas in EUV source spectrum for higher power do not influence imaging. It will also be shown that resulting variations in DUV do not affect imaging performance significantly, provided that a suitable reticle black border is used. In short, spectral purity performance is not a bottleneck for increasing power of EUV systems to well above 250W.

With the introduction of the NXE:3400B scanner, ASML has brought extreme ultraviolet lithography (EUV) to high-volume manufacturing (HVM). The high-EUV power of >200 W being realized with this system satisfies the throughput requirements of HVM, but also requires reconsideration of the imaging aspects of spectral purity, both from the details of the EUV emission spectrum and from the deep-ultraviolet (DUV) emission. We present simulation and experimental results for the spectral purity of high-power EUV systems and the imaging impact of this, both for the case of with and without a pellicle. Also, possible controls for spectral purity will be discussed, and an innovative method will be described to measure imaging impact of varying conversion efficiency (CE) and DUV. It will be shown that CE optimization toward higher source power leads to reduction in relative DUV content, and the small deltas in EUV source spectrum for higher power do not influence imaging. It will also be shown that resulting variations in DUV do not affect imaging performance significantly, provided that a suitable reticle black border is used. In summary, spectral purity performance is found to enable current and upcoming nodes of EUV lithography and to not be a bottleneck for further increasing power of EUV systems to well above 250 W.

We evaluated a contact metrology instrument used in chemical–mechanical polishing (CMP) systems for high-volume manufacture and examined in situ coefficient of friction (COF) monitoring to identify the tribology of CMP, and subsequently to determine the useful lifespan of consumables. The results showed that the direct measurement of the wear of the pad allowed for an accurate determination of both pad thickness and the ideal time to replace the pad and conditioner disk based on pad wear rate. We also presented a clear correlation between the working grid area of the conditioner disk and the tribological behavior of the pad break-in procedure, leading to the result showing that the variation in tungsten film removal rate decreased as the working grid density of the conditioner disk increased. This study has proven the effectiveness of measuring friction force for better CMP control.

Agility in manufacturing requires a quick response to the changes in quantity of products without losing productivity. A high‐volume flexible manufacturing system (HV‐FMS) attains the high flexibility as well as the high volume production. We consider in this paper the energy‐saving effect of HV‐FMS from the viewpoint of consumed electric power. We take a production system of cylinder heads for automobile engines as a subject in this study, and draw a comparison of the energy‐saving effect between HV‐FMS and flexible transfer line to verify the effectiveness of HV‐FMS. Moreover, we discuss the economic effect of high‐speed processing at HV‐FMS. We measure the energy‐saving effect by high‐speed processing and give the permissible level for additional tooling cost.

Production quality improvement during manufacturing systems ramp-up

Highly automated manufacturing systems offer several advantages and are widely introduced as a strategy to improve the performance of manufacturing organizations. Various forms of automated equipment, such as industrial robots or flexible automatic machines, are used extensively in high-volume industrial production. Especially for flow production systems automation has advanced considerably. This type of production system can, for instance, be found in the automotive, home appliance, or electronics industry where highly automated flow lines are mainly implemented for safety, quality, and productivity reasons. A significant challenge in the operation of highly automated assembly lines is the occurrence of equipment failures which impair the throughput rate. Therefore, buffer space is allocated between the stations of an assembly line in order to achieve a desired throughput rate in spite of equipment failures. However, the installation of buffer space requires considerable investments and also leads to an increase of the average work-in-process inventory in the line. A different approach to achieve a desired throughput rate despite equipment failures is a redundant configuration, in which downstream stations automatically take over the operations of failed stations in the event of failure. The throughput loss in these situations mainly depends on the level of redundancy designed into the system. We present an assembly line balancing model for automated assembly lines which maximizes the lines’ level of redundancy for a given number of stations. In a numerical analysis we demonstrate the effectiveness of the approach and show that a redundant configuration allows for significant reductions of required buffer sizes in flow lines with unreliable equipment for a given throughput rate.

Within the advanced packaging technologies there is an increasing demand for very high I/O count solutions to fulfill requirements of high performance computing applications like big data analysis. Thus, the density of lateral and vertical interconnects is being pushed to its limits to achieve a minimum delay in communication between chips or chiplets from different technology nodes. Here we focus on dry etch technology as an approach to overcome the difficulties of currently used processes for the formation of vertical interconnects (vias) in organic buildup films. Nowadays, laser drilling into the organic dielectric is the state-of-the-art technology to prepare vertical interconnects between the Cu layers. However, drawbacks like sequential processing, limited control of sidewall smoothness or registration accuracy become extremely challenging when millions of sub-vias have to be realized on 600 mm2 panels. One alternative technique to address the need of forming steep microstructures in various materials is deep reactive-ion etching (DRIE). In this paper we analyze how DRIE could be applied for via formation in silica-filled organic dielectric build-up films. Our approach included a metallic hard mask for material-selective etching and for generating various via diameters. For our experiments, a dual frequency capacitive coupled plasma (CCP) tool was used. The plasma etch module was designed for panel-level substrates up to size and was integrated into a high volume manufacturing system. We investigated the influence of different gas mixtures, power settings on etch rate, selectivity (e.g. on silica and organic), directionality, uniformity and homogeneity. The overall compatibility and implications of the dry etching approach for the semi-additive process and redistribution layer formation have been discussed.

A heuristic is derived for real-time dynamic lot sizing at the bottleneck of a high volume manufacturer of many pan types. This bottleneck resource is subject to significant, random setup times. The problem is motivated by the scheduling requirements of a medical device manufacturing division of Johnson & Johnson, where meeting a common due date for all the current week's production is critical. The lot-sizing heuristic is one component of a hierarchical dispatching policy in which lot sequencing dominates lot sizing. A sample problem is developed and modelled as a dynamic program in order to demonstrate the form of an optimal solution. Numerical tests are provided which compare the dynamic program policy, a derived heuristic and other controllers. The results indicate the possibility of closed feedback control as an efficient method for dispatching pans. A prototype controller which was developed based on the heuristic control policy is briefly described.